Home
last modified time | relevance | path

Searched refs:CLK_PWM1_SEL_SHIFT (Results 1 – 18 of 18) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rv1103b.h217 CLK_PWM1_SEL_SHIFT = 13, enumerator
218 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rv1106.h226 CLK_PWM1_SEL_SHIFT = 9, enumerator
227 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rk3506.h185 CLK_PWM1_SEL_SHIFT = 10, enumerator
186 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rv1126.h181 CLK_PWM1_SEL_SHIFT = 15, enumerator
182 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rk3528.h202 CLK_PWM1_SEL_SHIFT = 8, enumerator
203 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rv1126b.h374 CLK_PWM1_SEL_SHIFT = 8, enumerator
375 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rk3588.h245 CLK_PWM1_SEL_SHIFT = 12, enumerator
246 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rk3568.h460 CLK_PWM1_SEL_SHIFT = 8, enumerator
461 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
H A Dcru_rk3576.h308 CLK_PWM1_SEL_SHIFT = 8, enumerator
309 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1103b.c491 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1103b_pwm_get_clk()
532 src_clk << CLK_PWM1_SEL_SHIFT); in rv1103b_pwm_set_clk()
H A Dclk_rk3506.c738 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3506_pwm_get_rate()
783 (sel << CLK_PWM1_SEL_SHIFT) | in rk3506_pwm_set_rate()
H A Dclk_rv1106.c633 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1106_pwm_get_clk()
677 src_clk << CLK_PWM1_SEL_SHIFT); in rv1106_pwm_set_clk()
H A Dclk_rv1126.c276 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1126_pwm_get_pmuclk()
317 CLK_PWM1_SEL_XIN24M << CLK_PWM1_SEL_SHIFT); in rv1126_pwm_set_pmuclk()
328 CLK_PWM1_SEL_GPLL << CLK_PWM1_SEL_SHIFT); in rv1126_pwm_set_pmuclk()
H A Dclk_rk3528.c791 shift = CLK_PWM1_SEL_SHIFT; in rk3528_pwm_get_clk()
833 shift = CLK_PWM1_SEL_SHIFT; in rk3528_pwm_set_clk()
H A Dclk_rv1126b.c602 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1126b_pwm_get_clk()
667 (src_clk << CLK_PWM1_SEL_SHIFT) | in rv1126b_pwm_set_clk()
H A Dclk_rk3588.c582 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3588_pwm_get_clk()
629 src_clk << CLK_PWM1_SEL_SHIFT); in rk3588_pwm_set_clk()
H A Dclk_rk3576.c629 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3576_pwm_get_clk()
672 src_clk << CLK_PWM1_SEL_SHIFT); in rk3576_pwm_set_clk()
H A Dclk_rk3568.c1170 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3568_pwm_get_clk()
1209 src_clk << CLK_PWM1_SEL_SHIFT); in rk3568_pwm_set_clk()