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Searched refs:_reg (Results 1 – 25 of 25) sorted by relevance

/rk3399_ARM-atf/include/drivers/cadence/
H A Dcdns_nand.h15 #define FIELD_GET(_mask, _reg) \ argument
17 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
134 #define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \ argument
135 + (CNF_CMDREG_##_reg))
186 #define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \ argument
187 + (CNF_CTRLCFG_##_reg))
200 #define CNF_DI(_reg) (CNF_DI_REG_BASE \ argument
201 + (CNF_DI_##_reg))
222 #define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \ argument
223 + (CNF_CTRLPARAM_##_reg))
[all …]
H A Dcdns_combo_phy.h143 #define CP_DLL(_reg) (CP_DLL_REG_BASE \ argument
144 + (CP_DLL_##_reg))
158 #define CP_CTB(_reg) (CP_CTB_REG_BASE \ argument
159 + (CP_CTB_##_reg))
206 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ argument
207 (SDMMC_CDN_##_reg))
H A Dcdns_sdmmc.h339 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ argument
340 (SDMMC_CDN_##_reg))
/rk3399_ARM-atf/include/lib/cpus/aarch64/
H A Dcpu_macros.S148 .macro cpu_check_csv2 _reg _label
149 mrs \_reg, id_aa64pfr0_el1
150 ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
162 cmp \_reg, #4 /* Only values 0 to 3 are expected */
166 cmp \_reg, #0
356 .macro sysreg_bit_set _reg:req, _bit:req, _assert=1
357 mrs x1, \_reg
359 msr \_reg, x1
368 .macro sysreg_bit_clear _reg:req, _bit:req
369 mrs x1, \_reg
[all …]
/rk3399_ARM-atf/include/arch/aarch32/
H A Dasm_macros.S19 #define TLB_INVALIDATE(_reg, _coproc) \ argument
20 stcopr _reg, _coproc; \
22 stcopr _reg, _coproc
24 #define TLB_INVALIDATE(_reg, _coproc) \ argument
25 stcopr _reg, _coproc
135 .macro mov_imm _reg, _val
137 mov \_reg, #(\_val)
139 movw \_reg, #((\_val) & 0xffff)
140 movt \_reg, #((\_val) >> 16)
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_noc.h21 #define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ argument
22 + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
24 #define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ argument
25 + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
H A Dsocfpga_system_manager.h33 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
34 + (SOCFPGA_SYSMGR_##_reg))
H A Dsocfpga_reset_manager.h233 #define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE + (SOCFPGA_RSTMGR_##_reg)) argument
234 #define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) argument
H A Dsocfpga_f2sdram_manager.h45 #define SOCFPGA_F2SDRAMMGR(_reg) (SOCFPGA_F2SDRAMMGR_REG_BASE \ argument
46 + (SOCFPGA_F2SDRAMMGR_##_reg))
/rk3399_ARM-atf/include/arch/aarch64/
H A Dasm_macros.S170 .macro _mov_imm16 _reg, _val, _shift
173 movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
175 mov \_reg, \_val & (0xffff << \_shift)
186 .macro mov_imm _reg, _val
188 mov \_reg, #0
190 _mov_imm16 \_reg, (\_val), 0
191 _mov_imm16 \_reg, (\_val), 16
192 _mov_imm16 \_reg, (\_val), 32
193 _mov_imm16 \_reg, (\_val), 48
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.h26 #define CLKMGR(_reg) (CLKMGR_BASE + (CLKMGR_##_reg)) argument
60 #define CLKMGR_MAINPLL(_reg) (CLKMGR_MAINPLL_BASE + \ argument
61 (CLKMGR_MAINPLL_##_reg))
90 #define CLKMGR_PERPLL(_reg) (CLKMGR_PERPLL_BASE + \ argument
91 (CLKMGR_PERPLL_##_reg))
112 #define CLKMGR_ALTERA(_reg) (CLKMGR_ALTERA_BASE + \ argument
113 (CLKMGR_ALTERA_##_reg))
H A Dagilex5_pinmux.h140 #define SOCFPGA_PINUMX_USEFPGA(_reg) (AGX5_PINMUX_EMAC0_USEFPGA \ argument
141 + SOCFPGA_PINMUX_##_reg)
195 #define SOCFPGA_PINMUX(_reg) (SOCFPGA_PINMUX_REG_BASE \ argument
196 + (SOCFPGA_PINMUX_##_reg))
H A Dagilex5_system_manager.h236 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
237 + (SOCFPGA_ECC_QSPI_##_reg))
238 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
239 + (SOCFPGA_SYSMGR_##_reg))
H A Dagilex5_power_manager.h82 #define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \ argument
83 (AGX5_PWRMGR_##_reg))
H A Dagilex5_memory_controller.h172 #define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \ argument
173 + (SOCFPGA_MEMCTRL_##_reg))
H A Dagilex5_iossm_mailbox.h18 #define FIELD_GET(_mask, _reg) \ argument
20 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dplat_common.h12 #define FIELD_GET(_mask, _reg) \ argument
14 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Ds10_system_manager.h198 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
199 + (SOCFPGA_ECC_QSPI_##_reg))
201 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
202 + (SOCFPGA_SYSMGR_##_reg))
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_system_manager.h199 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
200 + (SOCFPGA_ECC_QSPI_##_reg))
202 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
203 + (SOCFPGA_SYSMGR_##_reg))
H A Dagilex_memory_controller.h172 #define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \ argument
173 + (SOCFPGA_MEMCTRL_##_reg))
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dn5x_system_manager.h202 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ argument
203 + (SOCFPGA_ECC_QSPI_##_reg))
205 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ argument
206 + (SOCFPGA_SYSMGR_##_reg))
/rk3399_ARM-atf/plat/imx/imx8ulp/scmi/
H A Dscmi_pd.c138 #define PWR_DOMAIN(_name, _reg, _psw_parent, _sram_parent, \ argument
142 .reg = _reg, \
/rk3399_ARM-atf/lib/el3_runtime/aarch64/
H A Dcontext.S565 .macro get_per_world_context _reg:req
573 mov \_reg, x9
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp13.c1186 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ argument
1190 .reg_pllxcr = (_reg),\
1676 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ argument
1680 .reg_pllxcr = (_reg),\
H A Dclk-stm32mp2.c711 #define CLK_PLL_CFG(_idx, _clk_id, _reg)\ argument
714 .reg_pllxcfgr1 = (_reg),\