120335ca8SHadi Asyrafi /* 276184031SJit Loon Lim * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3*8a0a006aSJit Loon Lim * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 420335ca8SHadi Asyrafi * 520335ca8SHadi Asyrafi * SPDX-License-Identifier: BSD-3-Clause 620335ca8SHadi Asyrafi */ 720335ca8SHadi Asyrafi 820335ca8SHadi Asyrafi #ifndef SOCFPGA_SYSTEMMANAGER_H 920335ca8SHadi Asyrafi #define SOCFPGA_SYSTEMMANAGER_H 1020335ca8SHadi Asyrafi 1120335ca8SHadi Asyrafi #include "socfpga_plat_def.h" 1220335ca8SHadi Asyrafi 1320335ca8SHadi Asyrafi /* System Manager Register Map */ 1420335ca8SHadi Asyrafi 1520335ca8SHadi Asyrafi #define SOCFPGA_SYSMGR_SDMMC 0x28 1620335ca8SHadi Asyrafi 1720335ca8SHadi Asyrafi /* Field Masking */ 1820335ca8SHadi Asyrafi #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 19aea772ddSTien Hock Loh #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 2020335ca8SHadi Asyrafi 2111f4f030SSieu Mun Tang #define IDLE_DATA_LWSOC2FPGA BIT(4) 2211f4f030SSieu Mun Tang #define IDLE_DATA_SOC2FPGA BIT(0) 2320335ca8SHadi Asyrafi #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) 2420335ca8SHadi Asyrafi 257f9e9e4bSJit Loon Lim #define SYSMGR_QSPI_REFCLK_MASK GENMASK(27, 0) 267f9e9e4bSJit Loon Lim 27c703d752SSieu Mun Tang #define SYSMGR_ECC_OCRAM_MASK BIT(1) 28c703d752SSieu Mun Tang #define SYSMGR_ECC_DDR0_MASK BIT(16) 29c703d752SSieu Mun Tang #define SYSMGR_ECC_DDR1_MASK BIT(17) 30c703d752SSieu Mun Tang 3120335ca8SHadi Asyrafi /* Macros */ 3220335ca8SHadi Asyrafi 3320335ca8SHadi Asyrafi #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 3420335ca8SHadi Asyrafi + (SOCFPGA_SYSMGR_##_reg)) 3520335ca8SHadi Asyrafi 36ea906b9bSSieu Mun Tang /* Function Prototype */ 37ea906b9bSSieu Mun Tang uint32_t intel_hps_get_jtag_id(void); 38ea906b9bSSieu Mun Tang bool is_agilex5_A5F0(void); 39*8a0a006aSJit Loon Lim bool is_agilex5_A5F4(void); 40ea906b9bSSieu Mun Tang 4120335ca8SHadi Asyrafi #endif /* SOCFPGA_SYSTEMMANAGER_H */ 42