Merge "fix(intel): fix SDMMC driver when sdmclk running at 200MHz" into integration

Merge "fix(intel): fix eMMC driver issues in boot flow on agilex5" into integration

fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717

fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717afe1fa0de167aae532f8b8de03b1c
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correc

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.

Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.

Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.

eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.

Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes from topic "s32g274a/sd_support" into integration

* changes:
feat(s32g274a): move fip in a dedicated partition
feat(s32g274ardb): initialize the IO buffer
feat(s32g274ardb): init

Merge changes from topic "s32g274a/sd_support" into integration

* changes:
feat(s32g274a): move fip in a dedicated partition
feat(s32g274ardb): initialize the IO buffer
feat(s32g274ardb): initialize the uSDHC driver
feat(s32g274ardb): set the system counter rate
feat(s32g274ardb): init the generic timer for BL2
fix(nxp-mmc): handle response for CMD0
refactor(mmc): replace 0 with MMC_RESPONSE_NONE
feat(mmc): add define for no response

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feat(mmc): add define for no response

Introduce a new macro definition to represent the response type for
commands that do not expect a response. This is particularly applicable
to commands like Com

feat(mmc): add define for no response

Introduce a new macro definition to represent the response type for
commands that do not expect a response. This is particularly applicable
to commands like Command 0, which is used to reset the card and place it
into the idle state.

Change-Id: I6fe298504a7166ccd7e47c23f88945b2ce064cf9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "fix(intel): refactor SDMMC driver for Altera products" into integration

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update preloaded_bl33_base for legacy product" into integration

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the start

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.

SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.

Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge changes from topic "utils_fixes" into integration

* changes:
refactor(lib): rename GENMASK parameters
fix(lib): avoid CWE-190 for GENMASK macros
fix(lib): fix MISRA 12.2 violations for B

Merge changes from topic "utils_fixes" into integration

* changes:
refactor(lib): rename GENMASK parameters
fix(lib): avoid CWE-190 for GENMASK macros
fix(lib): fix MISRA 12.2 violations for BIT32 and BIT64 macros
fix(intel): remove redundant BIT_32 macro

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fix(intel): remove redundant BIT_32 macro

BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h

Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681e

fix(intel): remove redundant BIT_32 macro

BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h

Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681ee9af7d65e8eab5a0bf1d5236ecfed1a4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A

Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

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feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-

feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6

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