| #
12211eac |
| 25-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): clock manager PLL configuration for Agilex5 platform" into integration
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| #
e60bedd5 |
| 25-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): clock manager PLL configuration for Agilex5 platform
Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.
Change-Id: I3c5cbaf7a677
feat(intel): clock manager PLL configuration for Agilex5 platform
Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.
Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
show more ...
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| #
5d23325e |
| 24-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): update BL2 platform specific functions" into integration
|
| #
fa1e92c6 |
| 24-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): update BL2 platform specific functions
Update and initialize the BL2 EL3 functions for agilex5
platform.
Change-Id: I673c622dfe4ff71d77edfa0866ebf6cd7163d793
Signed-off-by: Girisha Den
feat(intel): update BL2 platform specific functions
Update and initialize the BL2 EL3 functions for agilex5
platform.
Change-Id: I673c622dfe4ff71d77edfa0866ebf6cd7163d793
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
show more ...
|
| #
3393060c |
| 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
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| #
1b1a3eb1 |
| 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): clock manager support for Agilex5 SoC FPGA
This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
feat(intel): clock manager support for Agilex5 SoC FPGA
This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Standardized handoff handler.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b
show more ...
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