111f4f030SSieu Mun Tang /* 2*9b8d813cSJit Loon Lim * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 311f4f030SSieu Mun Tang * 411f4f030SSieu Mun Tang * SPDX-License-Identifier: BSD-3-Clause 511f4f030SSieu Mun Tang */ 611f4f030SSieu Mun Tang 711f4f030SSieu Mun Tang #ifndef SOCFPGA_F2SDRAMMANAGER_H 811f4f030SSieu Mun Tang #define SOCFPGA_F2SDRAMMANAGER_H 911f4f030SSieu Mun Tang 1011f4f030SSieu Mun Tang #include "socfpga_plat_def.h" 1111f4f030SSieu Mun Tang 1211f4f030SSieu Mun Tang /* FPGA2SDRAM Register Map */ 1311f4f030SSieu Mun Tang #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGINSTATUS0 0x14 1411f4f030SSieu Mun Tang #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTCLR0 0x54 1511f4f030SSieu Mun Tang #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTSET0 0x50 1611f4f030SSieu Mun Tang 17*9b8d813cSJit Loon Lim #define FLAGOUTCLR0_F2SDRAM0_ENABLE (BIT(8)) 1811f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM0_ENABLE (BIT(1)) 1911f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM1_ENABLE (BIT(4)) 2011f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM2_ENABLE (BIT(7)) 2111f4f030SSieu Mun Tang 2211f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM0_IDLEREQ (BIT(0)) 2311f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM1_IDLEREQ (BIT(3)) 2411f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM2_IDLEREQ (BIT(6)) 259ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM0_IDLEACK (BIT(1)) 269ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM1_IDLEACK (BIT(5)) 279ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM2_IDLEACK (BIT(9)) 289ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM0_CMDIDLE (BIT(2)) 299ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM1_CMDIDLE (BIT(6)) 309ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM2_CMDIDLE (BIT(10)) 319ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM0_NOCIDLE (BIT(0)) 329ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM1_NOCIDLE (BIT(4)) 339ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM2_NOCIDLE (BIT(8)) 349ce82519SAng Tien Sung 3511f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN (BIT(2)) 3611f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN (BIT(5)) 3711f4f030SSieu Mun Tang #define FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN (BIT(8)) 3811f4f030SSieu Mun Tang 399ce82519SAng Tien Sung #define FLAGINSTATUS_F2SOC_RESPEMPTY (BIT(3)) 409ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM0_RESPEMPTY (BIT(3)) 419ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM1_RESPEMPTY (BIT(7)) 429ce82519SAng Tien Sung #define FLAGINSTATUS_F2SDRAM2_RESPEMPTY (BIT(11)) 439ce82519SAng Tien Sung #define FLAGINSTATUS_F2S_FM_TRACKERIDLE (BIT(4)) 4411f4f030SSieu Mun Tang 4511f4f030SSieu Mun Tang #define SOCFPGA_F2SDRAMMGR(_reg) (SOCFPGA_F2SDRAMMGR_REG_BASE \ 4611f4f030SSieu Mun Tang + (SOCFPGA_F2SDRAMMGR_##_reg)) 4711f4f030SSieu Mun Tang 4811f4f030SSieu Mun Tang #endif /* SOCFPGA_F2SDRAMMGR_H */ 49