History log of /rk3399_ARM-atf/plat/intel/soc/agilex5/include/agilex5_iossm_mailbox.h (Results 1 – 6 of 6)
Revision Date Author Comments
# aac2ee38 21-Aug-2025 Mark Dykes <mark.dykes@arm.com>

Merge "fix(intel): iossm v2 enhancement refactor" into integration


# f1b1fae9 17-Jun-2025 Jit Loon Lim <jit.loon.lim@altera.com>

fix(intel): iossm v2 enhancement refactor

This patch is to used to update iossm v2 enhancement.
The major change is to replace io_mb_req to
mmio_read.
Next is to refactor the code.

Change-Id: Id084

fix(intel): iossm v2 enhancement refactor

This patch is to used to update iossm v2 enhancement.
The major change is to replace io_mb_req to
mmio_read.
Next is to refactor the code.

Change-Id: Id0842392f362e30252f1ac9f32797d8d3a419997
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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# d0abef9f 07-Aug-2025 Mark Dykes <mark.dykes@arm.com>

Merge "fix(intel): support DDR In-line and Out-of-Band ECC handling" into integration


# 92d22776 19-Mar-2025 Girisha Dengi <girisha.dengi@intel.com>

fix(intel): support DDR In-line and Out-of-Band ECC handling

Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the s

fix(intel): support DDR In-line and Out-of-Band ECC handling

Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the system accordingly.

Change-Id: I5138124e0d68dc8c93c98ae71eb13a77e49fd682
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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# 63446df6 16-Oct-2024 Mark Dykes <mark.dykes@arm.com>

Merge "feat(intel): update Agilex5 DDR and IOSSM driver" into integration


# ce21a1a9 26-Aug-2024 Sieu Mun Tang <sieu.mun.tang@intel.com>

feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2

feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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