1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef AGX5_SOCFPGA_SYSTEMMANAGER_H 8 #define AGX5_SOCFPGA_SYSTEMMANAGER_H 9 10 #include "socfpga_plat_def.h" 11 12 /* System Manager Register Map */ 13 #define SOCFPGA_SYSMGR_SILICONID_1 0x00 14 #define SOCFPGA_SYSMGR_SILICONID_2 0x04 15 #define SOCFPGA_SYSMGR_WDDBG 0x08 16 #define SOCFPGA_SYSMGR_MPU_STATUS 0x10 17 #define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C 18 #define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34 19 #define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38 20 #define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C 21 #define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40 22 #define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */ 23 #define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */ 24 #define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */ 25 #define SOCFPGA_SYSMGR_TSN_0_ACE 0x50 26 #define SOCFPGA_SYSMGR_TSN_1_ACE 0x54 27 #define SOCFPGA_SYSMGR_TSN_2_ACE 0x58 28 #define SOCFPGA_SYSMGR_FPGA_BRIDGE_CTRL 0x5C 29 #define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68 30 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C 31 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 32 #define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74 33 #define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78 34 #define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C 35 #define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80 36 #define SOCFPGA_SYSMGR_OSC_TRIM 0x84 37 #define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88 38 #define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C 39 #define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90 40 #define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94 41 #define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98 42 #define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C 43 #define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0 44 /* NOC configuration value */ 45 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0 46 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4 47 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8 48 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC 49 #define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0 50 #define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4 51 #define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8 52 #define SOCFPGA_SYSMGR_FPGA_CFG 0xDC 53 #define SOCFPGA_SYSMGR_GPO 0xE4 54 #define SOCFPGA_SYSMGR_GPI 0xE8 55 #define SOCFPGA_SYSMGR_MPU 0xF0 56 #define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4 57 #define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8 58 #define SOCFPGA_SYSMGR_DFI_INTF 0xFC 59 #define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100 60 #define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104 61 #define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108 62 #define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C 63 #define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 64 #define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114 65 #define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118 66 #define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C 67 #define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120 68 #define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124 69 #define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128 70 #define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C 71 #define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130 72 #define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134 73 #define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138 74 #define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C 75 #define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140 76 #define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144 77 #define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148 78 #define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C 79 #define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150 80 #define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154 81 #define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158 82 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C 83 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160 84 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164 85 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168 86 #define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C 87 #define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170 88 #define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174 89 #define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178 90 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C 91 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180 92 #define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184 93 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188 94 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C 95 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190 96 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194 97 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198 98 #define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C 99 #define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0 100 #define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4 101 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8 102 #define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC 103 #define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0 104 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4 105 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8 106 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC 107 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0 108 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4 109 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8 110 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC 111 #define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0 112 #define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0 113 #define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4 114 115 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 116 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 117 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 118 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C 119 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210 120 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214 121 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218 122 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C 123 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 124 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 125 #define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228 126 #define SOCFPGA_SYSMGR_MPFE_STATUS 0x22C 127 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230 128 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234 129 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238 130 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C 131 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240 132 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244 133 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248 134 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C 135 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250 136 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254 137 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258 138 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C 139 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260 140 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264 141 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268 142 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C 143 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270 144 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274 145 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278 146 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C 147 #define SOCFPGA_SYSMGR_SDM_BE_AWADDR_REMAP 0x280 148 #define SOCFPGA_SYSMGR_SDM_BE_ARADDR_REMAP 0x284 149 150 /* QSPI ECC from SDM register */ 151 #define SOCFPGA_ECC_QSPI_CTRL 0x08 152 #define SOCFPGA_ECC_QSPI_INITSTAT 0x0C 153 #define SOCFPGA_ECC_QSPI_ERRINTEN 0x10 154 #define SOCFPGA_ECC_QSPI_ERRINTENS 0x14 155 #define SOCFPGA_ECC_QSPI_ERRINTENR 0x18 156 #define SOCFPGA_ECC_QSPI_INTMODE 0x1C 157 #define SOCFPGA_ECC_QSPI_INTSTAT 0x20 158 #define SOCFPGA_ECC_QSPI_INTTEST 0x24 159 #define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78 160 #define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C 161 #define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80 162 163 /* IOSSM mailbox address */ 164 #define IOSSM_CMD_PARAM 0x18400438 165 #define IOSSM_CMD_TRIG_OP 0x1840043C 166 #define IOSSM_CMD_RESP_STATUS 0x1840045C 167 168 #define DMA0_STREAM_CTRL_REG 0x10D1217C 169 #define DMA1_STREAM_CTRL_REG 0x10D12180 170 #define SDM_STREAM_CTRL_REG 0x10D12184 171 #define USB2_STREAM_CTRL_REG 0x10D12188 172 #define USB3_STREAM_CTRL_REG 0x10D1218C 173 #define SDMMC_STREAM_CTRL_REG 0x10D12190 174 #define NAND_STREAM_CTRL_REG 0x10D12194 175 #define ETR_STREAM_CTRL_REG 0x10D12198 176 #define TSN0_STREAM_CTRL_REG 0x10D1219C 177 #define TSN1_STREAM_CTRL_REG 0x10D121A0 178 #define TSN2_STREAM_CTRL_REG 0x10D121A4 179 180 /* Stream ID configuration value for Agilex5 */ 181 #define TSN0 0x00010001 182 #define TSN1 0x00020002 183 #define TSN2 0x00030003 184 #define NAND 0x00040004 185 #define SDMMC 0x00050005 186 #define USB0 0x00060006 187 #define USB1 0x00070007 188 #define DMA0 0x00080008 189 #define DMA1 0x00090009 190 #define SDM 0x000A000A 191 #define CORE_SIGHT_DEBUG 0x000B000B 192 193 /* JTAG ID value for Agilex5 */ 194 #define A590_JTAG_ID 0x9000 195 #define A594_JTAG_ID 0x40009000 196 #define A5C0_JTAG_ID 0xC000 197 #define A5C4_JTAG_ID 0x4000C000 198 #define A5D0_JTAG_ID 0xD000 199 #define A5D4_JTAG_ID 0x4000D000 200 #define A5F0_JTAG_ID 0xC000 201 #define A5F4_JTAG_ID 0x4000C000 202 #define A510_JTAG_ID 0x1000 203 #define A514_JTAG_ID 0x40001000 204 #define A530_JTAG_ID 0x3000 205 #define A534_JTAG_ID 0x40003000 206 #define JTAG_ID_MASK 0xF000F000 207 208 /* Field Masking */ 209 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 210 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 211 212 #define SYSMGR_F2S_BRIDGE_CTRL_EN BIT(0) 213 #define SYSMGR_SOC_BRIDGE_CTRL_EN BIT(0) 214 #define SYSMGR_LWSOC_BRIDGE_CTRL_EN BIT(1) 215 #define IDLE_DATA_LWSOC2FPGA BIT(4) 216 #define IDLE_DATA_SOC2FPGA BIT(0) 217 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA \ 218 | IDLE_DATA_SOC2FPGA) 219 #define SYSMGR_ECC_OCRAM_MASK BIT(1) 220 #define SYSMGR_ECC_DDR0_MASK BIT(16) 221 #define SYSMGR_ECC_DDR1_MASK BIT(17) 222 223 #define WSTREAMIDEN_REG_CTRL BIT(0) 224 #define RSTREAMIDEN_REG_CTRL BIT(1) 225 #define WMMUSECSID_REG_VAL BIT(4) 226 #define RMMUSECSID_REG_VAL BIT(5) 227 228 #define SYSMGR_USB3_MISC0_RST_PUL_OVRD BIT(12) 229 #define SYSMGR_USB3_MISC0_PORT_OVR_CURR_PIPE_PWR BIT(14) 230 231 /* Macros */ 232 #define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \ 233 + (SOCFPGA_ECC_QSPI_##_reg)) 234 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 235 + (SOCFPGA_SYSMGR_##_reg)) 236 #define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL \ 237 | RSTREAMIDEN_REG_CTRL 238 #define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL \ 239 | RSTREAMIDEN_REG_CTRL \ 240 | WMMUSECSID_REG_VAL \ 241 | RMMUSECSID_REG_VAL 242 243 #endif /* AGX5_SOCFPGA_SYSTEMMANAGER_H */ 244