Merge changes I1bb556a8,Ie450acf7 into integration

* changes:
fix(intel): remove wfi polling when performing cpu on
fix(intel): fix socfpga_psci for cpu on off function

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will ca

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will cause
polling timeout since the CPU state is uncertain.

The CPU ON function will still work by removing this
check.

Change-Id: I1bb556a83ca16e122dfa35343de3e7cc39c5b678
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.

fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): update Agilex5 BL2 init flow and other misc changes" into integration

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc u

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A

Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

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feat(intel): power manager for Agilex5 SoC FPGA

This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5

feat(intel): power manager for Agilex5 SoC FPGA

This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3

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