| #
3393060c |
| 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
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| #
9b8d813c |
| 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): reset manager support for Agilex5 SoC FPGA
This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SD
feat(intel): reset manager support for Agilex5 SoC FPGA
This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC
2. Added EMULATOR support
3. Added WDT support
4. Updated product name -> Agilex5
5. Added SMP support
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11
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|
| #
49eccae9 |
| 12-Apr-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(intel): fix bridge disable and reset" into integration
|
| #
9ce82519 |
| 13-Mar-2023 |
Ang Tien Sung <tien.sung.ang@intel.com> |
feat(intel): fix bridge disable and reset
Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.
Signed-off-by: Ang Tie
feat(intel): fix bridge disable and reset
Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.
Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I651f3ec163d954e8efb0542ec33bce96e51992db
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| #
f0f631fd |
| 10-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration
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| #
11f4f030 |
| 05-May-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properl
feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.
The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21
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