| #
57c20e24 |
| 24-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): correct macro naming" into integration
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| #
815245e4 |
| 07-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): correct macro naming
Correct macro naming to meet define macro standard.
Change-Id: Id0a091d67ef879a0f4c048bd9c2169c603ff4ce9
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
55512649 |
| 27-Dec-2023 |
Sandrine Bailleux (on vacation) <sandrine.bailleux@arm.com> |
Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration
* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): suppor
Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration
* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux
show more ...
|
| #
8be16e44 |
| 18-Oct-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): support QSPI ECC Linux for Stratix10
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.
feat(intel): support QSPI ECC Linux for Stratix10
Add QSPI ECC new opcodes for Linux to access to SDM register
Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
show more ...
|
| #
816c27fb |
| 23-May-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes I38545567,I2f52d3ea into integration
* changes:
feat(intel): restructure sys mgr for S10/N5X
feat(intel): restructure sys mgr for Agilex
|
| #
b653f3ca |
| 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): restructure sys mgr for S10/N5X
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for
feat(intel): restructure sys mgr for S10/N5X
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I385455671413e154d04a879d33fdd774fcfefbd6
show more ...
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| #
3dcb94dd |
| 21-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi
intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
show more ...
|
| #
222519a0 |
| 21-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Modify non secure access function
Combine both peripheral and bridge non-secure access code
into a single callable function
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@int
intel: Modify non secure access function
Combine both peripheral and bridge non-secure access code
into a single callable function
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70
show more ...
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| #
1ab2dc1a |
| 09-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Remove redundant declarations." into integration
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| #
7a05f06a |
| 02-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Remove redundant declarations.
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.
Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by:
Remove redundant declarations.
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.
Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| #
5dbdf8e4 |
| 05-Sep-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration
|
| #
fea24b88 |
| 30-Jul-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.ha
intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
show more ...
|
| #
ec92cbcb |
| 11-Jul-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Merge "plat/intel: Fix SMPLSEL for MMC" into integration
|
| #
0943ea37 |
| 09-Jul-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
plat/intel: Fix SMPLSEL for MMC
MMC sample select needs to be set properly so that DWMMC clock can be
driven to 50Mhz
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I4a1dde4f6a1
plat/intel: Fix SMPLSEL for MMC
MMC sample select needs to be set properly so that DWMMC clock can be
driven to 50Mhz
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a
show more ...
|
| #
6ce30346 |
| 04-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1783 from thloh85-intel/integration_v2
plat: intel: Add BL2 support for Stratix 10 SoC
|
| #
9d82ef26 |
| 04-Feb-2019 |
Loh Tien Hock <tien.hock.loh@intel.com> |
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scru
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
show more ...
|