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Searched refs:BL31_LIMIT (Results 1 – 25 of 127) sorted by relevance

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/rk3399_ARM-atf/plat/renesas/rcar_gen5/include/
H A Dplat.ld.S16 PRAM (r) : ORIGIN = BL31_LIMIT - (DEVICE_SRAM_SIZE + DEVICE_SRAM_DATA_SIZE),
23 . = BL31_LIMIT - (DEVICE_SRAM_SIZE + DEVICE_SRAM_DATA_SIZE);
34 . = BL31_LIMIT - DEVICE_SRAM_DATA_SIZE;
43 ASSERT(__BL31_END__ <= (BL31_LIMIT - (DEVICE_SRAM_SIZE + DEVICE_SRAM_DATA_SIZE)),
/rk3399_ARM-atf/plat/renesas/rcar_gen4/include/
H A Dplat.ld.S16 PRAM (r) : ORIGIN = BL31_LIMIT - (DEVICE_SRAM_SIZE + DEVICE_SRAM_DATA_SIZE),
23 . = BL31_LIMIT - (DEVICE_SRAM_SIZE + DEVICE_SRAM_DATA_SIZE);
35 . = BL31_LIMIT - DEVICE_SRAM_DATA_SIZE;
43 ASSERT(__BL31_END__ <= (BL31_LIMIT - (DEVICE_SRAM_SIZE + DEVICE_SRAM_DATA_SIZE)),
/rk3399_ARM-atf/plat/renesas/common/include/
H A Dplat.ld.S14 PRAM (r): ORIGIN = BL31_LIMIT - DEVICE_SRAM_SIZE, LENGTH = DEVICE_SRAM_SIZE
20 . = BL31_LIMIT - DEVICE_SRAM_SIZE;
31 ASSERT(__BL31_END__ <= BL31_LIMIT - DEVICE_SRAM_SIZE,
/rk3399_ARM-atf/plat/allwinner/common/include/
H A Dplatform_def.h19 #define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000) macro
30 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ macro
43 #define SUNXI_SCP_BASE BL31_LIMIT
/rk3399_ARM-atf/plat/hisilicon/hikey/include/
H A Dhikey_layout.h80 #define BL31_LIMIT (0xF9898000) macro
89 #define BL32_SRAM_BASE BL31_LIMIT
90 #define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
/rk3399_ARM-atf/plat/aspeed/ast2700/include/
H A Dplatform_def.h43 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) macro
46 #define BL32_BASE BL31_LIMIT
/rk3399_ARM-atf/plat/brcm/board/stingray/include/
H A Dplatform_def.h147 #define BL31_LIMIT (BRCM_AP_TZC_DRAM1_BASE + \ macro
154 #define BL31_LIMIT (NOR_BASE_ADDR + NOR_SIZE) macro
157 #define SECURE_DDR_END_ADDRESS BL31_LIMIT
/rk3399_ARM-atf/plat/arm/board/arm_fpga/include/
H A Dplatform_def.h33 #define BL31_LIMIT UL(0x80070000) macro
36 #define BL31_LIMIT UL(0x01000000) macro
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/
H A Dplatform_def.h68 #define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */ macro
104 #define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
/rk3399_ARM-atf/plat/nxp/common/include/default/
H A Dplat_default_def.h91 #ifndef BL31_LIMIT
92 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) macro
/rk3399_ARM-atf/plat/xilinx/zynqmp/include/
H A Dplatform_def.h44 # define BL31_LIMIT U(0x100000000) macro
47 # define BL31_LIMIT U(0x80000) macro
51 # define BL31_LIMIT (UL(ZYNQMP_ATF_MEM_BASE) + U(ZYNQMP_ATF_MEM_SIZE)) macro
/rk3399_ARM-atf/bl31/
H A Dbl31.ld.S16 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
192 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
251 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
/rk3399_ARM-atf/plat/qti/kodiak/sc7280_chrome/inc/
H A Dplatform_def.h22 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) macro
/rk3399_ARM-atf/plat/xilinx/versal/include/
H A Dplatform_def.h39 # define BL31_LIMIT U(0x100000000) macro
42 # define BL31_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Dbl31_param.h24 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) macro
/rk3399_ARM-atf/plat/amd/versal2/include/
H A Dplatform_def.h47 # define BL31_LIMIT U(0xBC000000) macro
50 # define BL31_LIMIT U(MEM_BASE + MEM_SIZE) macro
/rk3399_ARM-atf/plat/nxp/common/setup/aarch64/
H A Dls_bl2_mem_params_desc.c43 .image_info.image_max_size = (BL31_LIMIT - BL31_BASE) +
47 .image_info.image_max_size = (BL31_LIMIT - BL31_BASE),
/rk3399_ARM-atf/plat/imx/imx8qx/
H A Dimx8qx_bl31_setup.c254 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) { in imx8_partition_resources()
269 if ((BL31_LIMIT - 1) < end) { in imx8_partition_resources()
270 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end); in imx8_partition_resources()
273 (sc_faddr_t)BL31_LIMIT, end); in imx8_partition_resources()
277 (sc_faddr_t)BL31_LIMIT, end); in imx8_partition_resources()
/rk3399_ARM-atf/plat/qemu/qemu_sbsa/include/
H A Dplatform_def.h152 #define BL31_BASE (BL31_LIMIT - BL31_SIZE)
153 #define BL31_LIMIT (BL1_RW_BASE - FW_HANDOFF_SIZE - \ macro
158 #define FW_HANDOFF_BASE BL31_LIMIT
180 #define TB_FW_CONFIG_BASE (BL31_LIMIT + FW_HANDOFF_SIZE)
/rk3399_ARM-atf/plat/xilinx/versal_net/include/
H A Dplatform_def.h46 # define BL31_LIMIT U(0xBC000000) macro
49 # define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE) macro
/rk3399_ARM-atf/plat/xilinx/zynqmp/
H A Dzynqmp_sdei.c20 uint64_t limit = BL31_LIMIT; in arm_validate_ns_entrypoint()
/rk3399_ARM-atf/plat/qti/kodiak/rb3gen2/inc/
H A Dplatform_def.h21 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) macro
/rk3399_ARM-atf/bl31/aarch64/
H A Dbl31_entrypoint.S52 _pie_fixup_size=BL31_LIMIT - BL31_BASE
68 _pie_fixup_size=BL31_LIMIT - BL31_BASE
/rk3399_ARM-atf/plat/xilinx/versal_net/
H A Dversal_net_sdei.c17 uintptr_t limit = BL31_LIMIT; in arm_validate_ns_entrypoint()
/rk3399_ARM-atf/plat/imx/imx8qm/
H A Dimx8qm_bl31_setup.c267 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) { in mx8_partition_resources()
282 if ((BL31_LIMIT - 1) < end) { in mx8_partition_resources()
283 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end); in mx8_partition_resources()
286 (sc_faddr_t)BL31_LIMIT, end); in mx8_partition_resources()
290 (sc_faddr_t)BL31_LIMIT, end); in mx8_partition_resources()

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