Merge "fix(versal): update integer const with suffix U" into integration

fix(versal): update integer const with suffix U

Versal: standardize unsigned integer constants to use suffix.
Updated all unsigned integer constants in the Versal platform
to use the unsigned suffix

fix(versal): update integer const with suffix U

Versal: standardize unsigned integer constants to use suffix.
Updated all unsigned integer constants in the Versal platform
to use the unsigned suffix (e.g., `10U`)
instead of the prefix style (e.g., `U(10)`) for consistency.

Change-Id: Ie4d20c18cccede20062d6189c1024acfb3a3dce0
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge changes from topic "xlnx_misra_fix_versal" into integration

* changes:
fix(versal): match function type as its declared
fix(versal): switch case has only one confirming clause
fix(versal

Merge changes from topic "xlnx_misra_fix_versal" into integration

* changes:
fix(versal): match function type as its declared
fix(versal): switch case has only one confirming clause
fix(versal): typecast operands to match data type
fix(versal): replace ull with ULL to fix misra violation
fix(versal): typecast operands to match data type
fix(versal): match function declaration with its definition
fix(versal): add external declaration

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fix(versal): replace ull with ULL to fix misra violation

This corrects the MISRA violation C2012-7.3:
The issue is because the numeric literal "1ull" uses a lowercase 'l'
to specify its type. 'l' ca

fix(versal): replace ull with ULL to fix misra violation

This corrects the MISRA violation C2012-7.3:
The issue is because the numeric literal "1ull" uses a lowercase 'l'
to specify its type. 'l' can be visually ambiguous when placed next
to digits, especially with '1', Replacing "ull" with "ULL" is avoids
the confusion and fixes the issue.

Change-Id: I204d90316ea3bfec314c284284a423618274c87b
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge changes from topic "xlnx_versal_custom_sip" into integration

* changes:
feat(versal): add hooks for mmap and early setup
refactor(zynqmp): refactor custom sip service

feat(versal): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory ma

feat(versal): add hooks for mmap and early setup

Add early setup hooks through custom_early_setup() and provide a
mechanism to support custom memory mapping, including the extension
of the memory map via custom_mmap_add(). This change may also
require alignment of the MAX_XLAT_TABLE and MAX_XLAT_TABLES macros.
These can be defined within the custom_pkg.mk makefile as follows:

MAX_MMAP_REGIONS := XY
$(eval $(call add_define,MAX_MMAP_REGIONS))
MAX_XLAT_TABLES := XZ
$(eval $(call add_define,MAX_XLAT_TABLES))

If PLATFORM_STACK_SIZE is not already defined, a default value
should be used. This allows for configurability of the stack size
across different interfaces, such as custom packages. The
custom_early_setup() function enables early low-level operations
to bring the system into a correct state. Support for a custom
SiP service is also added. A basic implementation of
custom_smc_handler() is provided by the platform, while the actual
definition is expected to be supplied by the custom package. This
feature is designed for use by external libraries, such as those
that require status checking. This code introduces a generic
framework for integrating custom logic via the
$(CUSTOM_PKG_PATH)/custom_pkg.mk makefile, including
optional support for custom SMC functionality, which is determined
by the custom package.

Change-Id: If9107b32c8c1ca4026d0a2980901e841fc6e03f7
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_fix_plat_invalid_entry" into integration

* changes:
fix(versal): handle invalid entry point in cpu hotplug scenario
fix(versal-net): handle invalid entry point in

Merge changes from topic "xlnx_fix_plat_invalid_entry" into integration

* changes:
fix(versal): handle invalid entry point in cpu hotplug scenario
fix(versal-net): handle invalid entry point in cpu hotplug scenario
fix(zynqmp): handle invalid entry point in cpu hotplug scenario

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fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by:

fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "idling-during-subsystem-restart" into integration

* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add

Merge changes from topic "idling-during-subsystem-restart" into integration

* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add new state to identify cpu power down
feat(xilinx): request cpu power down from reset
feat(xilinx): power down all cores on receiving cpu pwrdwn req
feat(xilinx): add handler for power down req sgi irq
feat(xilinx): add wrapper to handle cpu power down req
fix(versal-net): use arm common GIC handlers
fix(xilinx): rename macros to align with ARM

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Merge "feat(versal): extend platform address space sizes" into integration

feat(versal): extend platform address space sizes

The AMD-Xilinx Versal platform, currently only supports the OCM and
Low DDR address ranges in both physical and virtual address range.
To locate and

feat(versal): extend platform address space sizes

The AMD-Xilinx Versal platform, currently only supports the OCM and
Low DDR address ranges in both physical and virtual address range.
To locate and execute TF-A from High DDR and HBM address range,
expanding the address scope is necessary.

Depending on the BL31_BASE address both the platform physical and
virtual space sizes are selected.

Change-Id: I49112bff9eda44d924c5f49ea99aed9a8d5e5774
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ

feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ.

By default TF-A uses SGI 6 for CPU power down request. This can be
configurable through CPU_PWRDWN_SGI build flag.

e.g., If user wants to use SGI 7 instead of SGI 6 then provide build
flag CPU_PWRDWN_SGI=7

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd

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fix(xilinx): rename macros to align with ARM

Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id:

fix(xilinx): rename macros to align with ARM

Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2987ff2f612993fc80979f0179c04d316259ed1d

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Merge "fix(versal): type cast addresses to fix integer overflow" into integration

fix(versal): type cast addresses to fix integer overflow

Typecast the base and size arguments for build time as unsigned
integers and the limit derived from these two as an unsigned long
to prevent

fix(versal): type cast addresses to fix integer overflow

Typecast the base and size arguments for build time as unsigned
integers and the limit derived from these two as an unsigned long
to prevent size integer overflow issues during the build.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Iefc148e0091e8c8a4ca505691036c79528a558a4

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Merge changes from topic "xlnx_fix_plat_ocm_base" into integration

* changes:
fix(xilinx): update dtb when dtb address and tf-a ddr flow is used
fix(versal): use correct macro name for ocm base

Merge changes from topic "xlnx_fix_plat_ocm_base" into integration

* changes:
fix(xilinx): update dtb when dtb address and tf-a ddr flow is used
fix(versal): use correct macro name for ocm base address

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fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning

fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157

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Merge changes from topic "xlnx_dtb_modification" into integration

* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build tim

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes Ica1f9786,Ic96e3680 into integration

* changes:
fix(versal): fix BLXX memory limits for user defined values
fix(zynqmp): fix BLXX memory limits for user defined values

fix(versal): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
a

fix(versal): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

While at it fix all other occurences of predefined values that were
calculated with -1

Fixes: commit f91c3cb1df7d4 ("arm64: versal: Add support for new Xilinx Versal ACAPs")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ica1f97867b701e7fcd60ea8ea07d2ae96c485443

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Merge "style(xilinx): replace ARM by Arm in copyrights" into integration

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "set-wake-source-for-versal-net" into integration

* changes:
refactor(xilinx): move enum to common place
fix(xilinx): fix misra defects
fix(xilinx): remove unnecessary

Merge changes from topic "set-wake-source-for-versal-net" into integration

* changes:
refactor(xilinx): move enum to common place
fix(xilinx): fix misra defects
fix(xilinx): remove unnecessary condition
feat(versal): replace irq array with switch case
feat(versal-net): add support for set wakeup source
refactor(versal): move set wake src fn to common place

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Merge "refactor(xilinx): rename gic macros to make common" into integration