Merge changes from topic "xlnx_fix_plat_invalid_entry" into integration

* changes:
fix(versal): handle invalid entry point in cpu hotplug scenario
fix(versal-net): handle invalid entry point in

Merge changes from topic "xlnx_fix_plat_invalid_entry" into integration

* changes:
fix(versal): handle invalid entry point in cpu hotplug scenario
fix(versal-net): handle invalid entry point in cpu hotplug scenario
fix(zynqmp): handle invalid entry point in cpu hotplug scenario

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fix(zynqmp): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87
Signed-off-by:

fix(zynqmp): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refacto

Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refactor console to support transfer list
chore(xilinx): propagate error code
feat(versal2): retrieve DT address from transfer list
chore(versal2): move xfer-list file paths
fix(versal2): update transfer list as optional

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refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
o

refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
or makefile where XLNX_DT_CFG macro describe if system is DT driven or not.

Change-Id: Id45c03a950b62e83e91a50e0485eacdb233ba745
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_zynqmp_sizefixes" into integration

* changes:
fix(zynqmp): type cast addresses to fix overflow issue
fix: integer suffix macro definition

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflo

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflow issue during build.

For zynqmp platform, calculating the limit without typecasting results
in build error as follows

make -j DEBUG=0 RESET_TO_BL31=1 PLAT=zynqmp \
ZYNQMP_ATF_MEM_BASE=0x70000000 ZYNQMP_ATF_MEM_SIZE=0x10000000 \
XILINX_OF_BOARD_DTB_ADDR=0x100000 bl31

plat/xilinx/zynqmp/include/platform_def.h:51:62:
error: integer overflow in expression of type 'int' results
in '-2147483648' [-Werror=overflow]
51 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE)

Change-Id: Id093a50e748884d4fba65626e94f361f6c23cecc
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes Ica1f9786,Ic96e3680 into integration

* changes:
fix(versal): fix BLXX memory limits for user defined values
fix(zynqmp): fix BLXX memory limits for user defined values

fix(zynqmp): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
a

fix(zynqmp): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

Commit 9b4ed0af02a8 ("feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'")
applied a similar fix, but only in the predefined for BL31LIMIT/BASE.

While at it fix all other occurences of predefined values that were
calculated with -1

Fixes: 01555332faa48 ("zynqmp: Revise memory configuration options")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ic96e36808d01f6bb92e6839cec92fc52320dd3f3

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Merge "fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS" into integration

Merge "style(xilinx): replace ARM by Arm in copyrights" into integration

fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS

Remove unused PLAT_NUM_POWER_DOMAINS macro. Macro is referenced by
docs/design/psci-pd-tree.rst but it is not used in any calculation
that's why it

fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS

Remove unused PLAT_NUM_POWER_DOMAINS macro. Macro is referenced by
docs/design/psci-pd-tree.rst but it is not used in any calculation
that's why it is better to remove it.

Change-Id: I33f26cda6a4404061af5598ea4c751f64127e50a
Signed-off-by: Michal Simek <michal.simek@amd.com>

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style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "feat(zynqmp): make stack size configurable" into integration

feat(zynqmp): make stack size configurable

If PLATFORM_STACK_SIZE not already defined, use the default value of
PLATFORM_STACK_SIZE.
This makes the stack size value configurable for different interf

feat(zynqmp): make stack size configurable

If PLATFORM_STACK_SIZE not already defined, use the default value of
PLATFORM_STACK_SIZE.
This makes the stack size value configurable for different interface
like custom packages.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I87e9fcbfb4c4092378b1ac0ff8fb6d084495d320

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Merge "fix(zynqmp): conditional reservation of memory in DTB" into integration

fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This create

fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This creates an error condition in the use case where Device tree is
not present or it is present at a different location.

To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is
introduced. The TF-A will reserve the DDR memory only when a valid
DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired
DDR address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "feat(zynqmp): add hooks for mmap and early setup" into integration

feat(zynqmp): add hooks for mmap and early setup

Add early setup hooks (via custom_early_setup()) and provide a way
to cover custom memory mapping which includes extending memory map
via custom_mmap

feat(zynqmp): add hooks for mmap and early setup

Add early setup hooks (via custom_early_setup()) and provide a way
to cover custom memory mapping which includes extending memory map
via custom_mmap_add().

This likely also require to align MAX_XLAT_TABLE, MAX_XLAT_TABLES
macros. It can be done for example by defining these macros in
custom_pkg.mk
MAX_MMAP_REGIONS := XY
$(eval $(call add_define,MAX_MMAP_REGIONS))
MAX_XLAT_TABLES := XZ
$(eval $(call add_define,MAX_XLAT_TABLES))

custom_early_setup() can be used for early low level operations
related to setting up the system to correct state.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I61df6f9ba5af0bc97c430974fb10a2edde44f23d

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Merge changes from topic "xlnx_zynqmp_debug" into integration

* changes:
fix(zynqmp): with DEBUG=1 move bl31 to DDR range
fix(zynqmp): update MAX_XLAT_TABLES for DDR memory range

fix(zynqmp): with DEBUG=1 move bl31 to DDR range

Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootf

fix(zynqmp): with DEBUG=1 move bl31 to DDR range

Due to size constraints in OCM memory range keeping the bl31 with
DEBUG=1 overlaps with the memory range from other Firmware thus
affecting the bootflow on target.
bl31 binary can not be placed in OCM memory range when built with
DEBUG=1.
With DEBUG=1, by default bl31 is moved to DDR memory range
0x1000-0x7FFFF.
The user can provide a custom DDR memory range during build time using
the build parameters ZYNQMP_ATF_MEM_BASE and ZYNQMP_ATF_MEM_SIZE.

Change-Id: I167d5eadbae7c6d3ec9b32f494b0b1a819bea5b0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(zynqmp): update MAX_XLAT_TABLES for DDR memory range

An assert is observed when the bl31 is placed in DDR memory range and
DEBUG is also enabled. To resolve this, increase the size of
MAX_XLAT_T

fix(zynqmp): update MAX_XLAT_TABLES for DDR memory range

An assert is observed when the bl31 is placed in DDR memory range and
DEBUG is also enabled. To resolve this, increase the size of
MAX_XLAT_TABLES to 8 when bl31 is placed in DDR memory range.

Change-Id: I7d35cba01cd5c8cfc8aae987719b8fc39fcf76b0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "fix(zynqmp): move debug bl31 based address back to OCM" into integration

fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM an

fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.

Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24

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Merge "fix(zynqmp): move bl31 with DEBUG=1 back to OCM" into integration

fix(zynqmp): move bl31 with DEBUG=1 back to OCM

By default placing bl31 to addrexx 0x1000 is not good. Because this
location is used by U-Boot SPL. That's why move TF-A back to OCM where it
should b

fix(zynqmp): move bl31 with DEBUG=1 back to OCM

By default placing bl31 to addrexx 0x1000 is not good. Because this
location is used by U-Boot SPL. That's why move TF-A back to OCM where it
should be placed. BL31_BASE address exactly matches which requested address
for U-BOOT SPL boot flow.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I608c1b88baffec538c6ae528f057820e34971c4c

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