| #
fc189d95 |
| 02-Jul-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(ast2700): set up CPU clock frequency by SCU" into integration
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| #
e3d1bbdb |
| 18-Jun-2024 |
Kevin Chen <kevin_chen@aspeedtech.com> |
feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[
feat(ast2700): set up CPU clock frequency by SCU
Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL
2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL
Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
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| #
cf6371bc |
| 30-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "refactor(ast2700): update memory layout" into integration
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| #
e681f1b8 |
| 29-Aug-2023 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
refactor(ast2700): update memory layout
Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.
Minor:
- Use SZ_xx macro to define size for better readab
refactor(ast2700): update memory layout
Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.
Minor:
- Use SZ_xx macro to define size for better readability
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I6d8285bd675321f615bb67cdd27bb4b6cb4c8b16
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| #
032c6983 |
| 15-Jun-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration
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| #
85f199b7 |
| 02-Nov-2022 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
feat(ast2700): add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the doc
feat(ast2700): add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.
Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
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