1*ac44b9c7SSumit Garg /* 2*ac44b9c7SSumit Garg * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. 3*ac44b9c7SSumit Garg * 4*ac44b9c7SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5*ac44b9c7SSumit Garg */ 6*ac44b9c7SSumit Garg #ifndef PLATFORM_DEF_H 7*ac44b9c7SSumit Garg #define PLATFORM_DEF_H 8*ac44b9c7SSumit Garg 9*ac44b9c7SSumit Garg #include <kodiak_def.h> 10*ac44b9c7SSumit Garg 11*ac44b9c7SSumit Garg #define MAX_IO_HANDLES 2 12*ac44b9c7SSumit Garg #define MAX_IO_DEVICES 2 13*ac44b9c7SSumit Garg #define MAX_IO_BLOCK_DEVICES U(1) 14*ac44b9c7SSumit Garg 15*ac44b9c7SSumit Garg #define BL2_BASE 0x1c00e000 16*ac44b9c7SSumit Garg #define BL2_SIZE 0x100000 17*ac44b9c7SSumit Garg #define BL2_LIMIT (BL2_BASE + BL2_SIZE) 18*ac44b9c7SSumit Garg 19*ac44b9c7SSumit Garg #define BL31_BASE 0x1c200000 20*ac44b9c7SSumit Garg #define BL31_SIZE 0x00100000 21*ac44b9c7SSumit Garg #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 22*ac44b9c7SSumit Garg 23*ac44b9c7SSumit Garg #define BL32_BASE 0x1c300000 24*ac44b9c7SSumit Garg #define BL32_SIZE 0x00200000 25*ac44b9c7SSumit Garg #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 26*ac44b9c7SSumit Garg 27*ac44b9c7SSumit Garg #define BL33_BASE 0x9f800000 28*ac44b9c7SSumit Garg #define BL33_SIZE 0x00400000 29*ac44b9c7SSumit Garg 30*ac44b9c7SSumit Garg #define PLAT_QTI_FIP_IOBASE 0x9fc00000 31*ac44b9c7SSumit Garg #define PLAT_QTI_FIP_MAXSIZE 0x00400000 32*ac44b9c7SSumit Garg 33*ac44b9c7SSumit Garg #endif /* PLATFORM_DEF_H */ 34