1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include "def.h" 14 #include <plat_common.h> 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #ifndef PLATFORM_STACK_SIZE 22 #define PLATFORM_STACK_SIZE U(0x440) 23 #endif 24 25 #define PLATFORM_CLUSTER_COUNT U(4) 26 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(2) /* 2 CPUs per cluster */ 27 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 29 30 #define E_INVALID_CORE_COUNT -1 31 #define E_INVALID_CLUSTER_COUNT -3 32 33 #define PLAT_MAX_PWR_LVL U(2) 34 #define PLAT_MAX_RET_STATE U(1) 35 #define PLAT_MAX_OFF_STATE U(2) 36 37 /******************************************************************************* 38 * BL31 specific defines. 39 ******************************************************************************/ 40 /* 41 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 42 * present). BL31_BASE is calculated using the current BL31 debug size plus a 43 * little space for growth. 44 */ 45 #ifndef MEM_BASE 46 # define BL31_BASE U(0xBBF00000) 47 # define BL31_LIMIT U(0xBC000000) 48 #else 49 # define BL31_BASE U(MEM_BASE) 50 # define BL31_LIMIT U(MEM_BASE + MEM_SIZE) 51 # ifdef MEM_PROGBITS_SIZE 52 # define BL31_PROGBITS_LIMIT U(MEM_BASE + \ 53 MEM_PROGBITS_SIZE) 54 # endif 55 #endif 56 57 /******************************************************************************* 58 * BL32 specific defines. 59 ******************************************************************************/ 60 #ifndef BL32_MEM_BASE 61 # define BL32_BASE U(0x01800000) 62 # define BL32_LIMIT U(0x09800000) 63 #else 64 # define BL32_BASE U(BL32_MEM_BASE) 65 # define BL32_LIMIT U(BL32_MEM_BASE + BL32_MEM_SIZE) 66 #endif 67 68 /******************************************************************************* 69 * BL33 specific defines. 70 ******************************************************************************/ 71 #ifndef PRELOADED_BL33_BASE 72 # define PLAT_ARM_NS_IMAGE_BASE U(0x40000000) 73 #else 74 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 75 #endif 76 77 /******************************************************************************* 78 * TSP specific defines. 79 ******************************************************************************/ 80 #define TSP_SEC_MEM_BASE BL32_BASE 81 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 82 83 /* ID of the secure physical generic timer interrupt used by the TSP */ 84 #define ARM_IRQ_SEC_PHY_TIMER U(29) 85 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 86 87 /******************************************************************************* 88 * Platform specific page table and MMU setup constants 89 ******************************************************************************/ 90 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 91 92 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 93 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 94 95 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 96 97 #define PLAT_OCM_BASE U(0xBBF00000) 98 #define PLAT_OCM_LIMIT U(0xBC000000) 99 100 #if TRANSFER_LIST 101 /* 102 * FIXME: This address should come from firmware before TF-A 103 * Having this to make sure the transfer list functionality works 104 */ 105 #define FW_HANDOFF_BASE U(0x1000000) 106 #define FW_HANDOFF_SIZE U(0x600000) 107 #endif 108 109 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 110 111 #ifndef MAX_MMAP_REGIONS 112 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 113 #define MAX_MMAP_REGIONS 11 114 #else 115 #define MAX_MMAP_REGIONS 10 116 #endif 117 #endif 118 119 #ifndef MAX_XLAT_TABLES 120 #define MAX_XLAT_TABLES U(12) 121 #endif 122 123 #define CACHE_WRITEBACK_SHIFT U(6) 124 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 125 126 #define PLAT_GICD_BASE_VALUE U(0xE2000000) 127 #define PLAT_GICR_BASE_VALUE U(0xE2060000) 128 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE_VALUE 129 #define PLAT_ARM_GICD_BASE PLAT_GICD_BASE_VALUE 130 131 /* 132 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 133 * terminology. On a GICv2 system or mode, the lists will be merged and treated 134 * as Group 0 interrupts. 135 */ 136 #define PLAT_IPI_IRQ 89 137 #define PLAT_VERSAL_IPI_IRQ PLAT_IPI_IRQ 138 139 #define PLAT_G1S_IRQ_PROPS(grp) \ 140 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_LEVEL) 142 143 #define PLAT_G0_IRQ_PROPS(grp) \ 144 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 145 GIC_INTR_CFG_EDGE), \ 146 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 147 GIC_INTR_CFG_EDGE) 148 149 #define IRQ_MAX 200U 150 151 #endif /* PLATFORM_DEF_H */ 152