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Searched refs:setbits_le32 (Results 1 – 25 of 274) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c69 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
72 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
74 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
76 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
78 setbits_le32(&phy->ctrl, BIT(19)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, BIT(18)); in sunxi_dw_hdmi_phy_init()
81 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
92 setbits_le32(&phy->ctrl, 0xf << 8); in sunxi_dw_hdmi_phy_init()
93 setbits_le32(&phy->ctrl, BIT(7)); in sunxi_dw_hdmi_phy_init()
[all …]
H A Dsunxi_display.c105 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
107 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
110 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
144 setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR); in sunxi_hdmi_ddc_do_command()
155 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START); in sunxi_hdmi_ddc_do_command()
225 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()
349 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0); in sunxi_frontend_init()
350 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0); in sunxi_frontend_init()
353 setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN); in sunxi_frontend_init()
364 setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY); in sunxi_frontend_init()
[all …]
H A Dlcdc.c46 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); in lcdc_enable()
48 setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); in lcdc_enable()
49 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); in lcdc_enable()
52 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); in lcdc_enable()
54 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); in lcdc_enable()
56 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); in lcdc_enable()
58 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); in lcdc_enable()
60 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); in lcdc_enable()
62 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); in lcdc_enable()
64 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); in lcdc_enable()
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c59 setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0); in broadwell_pch_early_init()
61 setbits_le32(RCB_REG(GCS), 1 << 5); in broadwell_pch_early_init()
99 setbits_le32(RCB_REG(0x3310), 0x0000002f); in pch_misc_init()
102 setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); in pch_misc_init()
103 setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); in pch_misc_init()
211 setbits_le32(RCB_REG(0x1100), 0x0000c13f); in pch_pm_init_magic()
241 setbits_le32(RCB_REG(0x0410), 0x00000003); in pch_pm_init_magic()
242 setbits_le32(RCB_REG(0x2618), 0x08000000); in pch_pm_init_magic()
243 setbits_le32(RCB_REG(0x2300), 0x00000002); in pch_pm_init_magic()
244 setbits_le32(RCB_REG(0x2600), 0x00000008); in pch_pm_init_magic()
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c230 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); in pch_power_options()
259 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); in cpt_pm_init()
261 setbits_le32(RCB_REG(0x228c), 1 << 0); in cpt_pm_init()
262 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); in cpt_pm_init()
263 setbits_le32(RCB_REG(0x0900), 1 << 14); in cpt_pm_init()
265 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); in cpt_pm_init()
266 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); in cpt_pm_init()
270 setbits_le32(RCB_REG(0x3340), 0xfffff); in cpt_pm_init()
271 setbits_le32(RCB_REG(0x3344), 1 << 1); in cpt_pm_init()
289 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ in cpt_pm_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dbroadwell_igd.c83 setbits_le32(regs + 0xa248, 0x00000016); in haswell_early_init()
105 setbits_le32(regs + 0xa090, 0x00000000); in haswell_early_init()
106 setbits_le32(regs + 0xa098, 0x03e80000); in haswell_early_init()
107 setbits_le32(regs + 0xa09c, 0x00280000); in haswell_early_init()
108 setbits_le32(regs + 0xa0a8, 0x0001e848); in haswell_early_init()
109 setbits_le32(regs + 0xa0ac, 0x00000019); in haswell_early_init()
118 setbits_le32(regs + 0xa0b0, 0x00000000); in haswell_early_init()
119 setbits_le32(regs + 0xa0b4, 0x000003e8); in haswell_early_init()
120 setbits_le32(regs + 0xa0b8, 0x0000c350); in haswell_early_init()
123 setbits_le32(regs + 0xa010, 0x000f4240); in haswell_early_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-stm32/stm32f4/
H A Dclock.c145 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); in configure_clocks()
154 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); in configure_clocks()
159 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); in configure_clocks()
162 setbits_le32(&STM32_RCC->cfgr, (( in configure_clocks()
172 setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC); in configure_clocks()
174 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); in configure_clocks()
181 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
245 setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN); in clock_setup()
248 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN); in clock_setup()
251 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN); in clock_setup()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c697 setbits_le32(&prcm_base->clksel_per, 0x000000FF); in prcm_init()
698 setbits_le32(&prcm_base->clksel_wkup, 1); in prcm_init()
711 setbits_le32(&prcm_base->iclken_usbhost, 1); in ehci_clocks_enable()
716 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); in ehci_clocks_enable()
718 setbits_le32(&prcm_base->iclken3_core, 0x00000004); in ehci_clocks_enable()
720 setbits_le32(&prcm_base->fclken3_core, 0x00000004); in ehci_clocks_enable()
731 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ in per_clocks_enable()
732 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ in per_clocks_enable()
733 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ in per_clocks_enable()
736 setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ in per_clocks_enable()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c34 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
49 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
98 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
116 setbits_le32(&dv_pll1_regs->pllctl, in dm365_pll2_init()
131 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); in dm365_pll2_init()
175 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
191 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ); in dm365_ddr_setup()
198 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN); in dm365_ddr_setup()
201 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK); in dm365_ddr_setup()
207 setbits_le32(&dv_sys_module_regs->vtpiocr, in dm365_ddr_setup()
[all …]
H A Dda850_lowlevel.c62 setbits_le32(&reg->pllctl, in da850_pll_init()
70 setbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
125 setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT); in da850_pll_init()
138 setbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
147 setbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
175 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
177 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
184 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); in da850_ddr_setup()
185 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); in da850_ddr_setup()
187 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); in da850_ddr_setup()
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dehci-vf.c69 setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE in usb_power_config()
76 setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE in usb_power_config()
100 setbits_le32(usb_cmd, UCMD_RESET); in usb_phy_enable()
105 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
116 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
126 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); in usb_oc_config()
127 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); in usb_oc_config()
183 setbits_le32(&ehci->usbmode, CM_DEVICE); in ehci_hcd_init()
185 setbits_le32(&ehci->portsc, USB_EN); in ehci_hcd_init()
187 setbits_le32(&ehci->usbmode, CM_HOST); in ehci_hcd_init()
[all …]
H A Dutmi-armada100.c25 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); in utmi_phy_init()
27 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); in utmi_phy_init()
30 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); in utmi_phy_init()
32 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); in utmi_phy_init()
42 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
47 setbits_le32(&phy_regs->utmi_tx, RCAL_START); in utmi_phy_init()
72 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); in utmi_init()
H A Dohci-lpc32xx.c126 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); in isp1301_configure()
138 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); in usbpll_setup()
141 setbits_le32(&clk_pwr->usb_ctrl, in usbpll_setup()
143 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); in usbpll_setup()
144 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); in usbpll_setup()
152 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); in usbpll_setup()
176 setbits_le32(&clk_pwr->usb_ctrl, in usb_cpu_init()
195 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); in usb_cpu_init()
207 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); in usb_cpu_init()
H A Dehci-omap.c100 setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI in omap_usbhs_hsic_init()
222 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); in omap_ehci_hcd_init()
227 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); in omap_ehci_hcd_init()
232 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); in omap_ehci_hcd_init()
241 setbits_le32(&reg, OMAP_P1_MODE_HSIC); in omap_ehci_hcd_init()
244 setbits_le32(&reg, OMAP_P2_MODE_HSIC); in omap_ehci_hcd_init()
257 setbits_le32(&reg, OMAP_P1_MODE_HSIC); in omap_ehci_hcd_init()
260 setbits_le32(&reg, OMAP_P2_MODE_HSIC); in omap_ehci_hcd_init()
263 setbits_le32(&reg, OMAP_P3_MODE_HSIC); in omap_ehci_hcd_init()
H A Dehci-exynos.c99 setbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
124 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_setup_usb_phy()
125 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_setup_usb_phy()
138 setbits_le32(&usb->ehcictrl, in exynos5_setup_usb_phy()
153 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); in exynos4412_setup_usb_phy()
177 setbits_le32(&usb->usbphyctrl0, in exynos5_reset_usb_phy()
190 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_reset_usb_phy()
191 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_reset_usb_phy()
196 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | in exynos4412_reset_usb_phy()
/OK3568_Linux_fs/u-boot/drivers/clk/
H A Dclk_stm32f7.c119 setbits_le32(&regs->cr, RCC_CR_HSION); in configure_clocks()
128 setbits_le32(&regs->cr, RCC_CR_HSEON); in configure_clocks()
132 setbits_le32(&regs->cfgr, (( in configure_clocks()
147 setbits_le32(&regs->cr, RCC_CR_PLLON); in configure_clocks()
152 setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN); in configure_clocks()
153 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN); in configure_clocks()
158 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN); in configure_clocks()
165 setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
242 setbits_le32(&regs->ahb1enr + offset, BIT(bit_index)); in stm32_clk_enable()
251 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); in clock_setup()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_arria10.c132 setbits_le32(&reset_manager_base->per1modrst, in socfpga_watchdog_disable()
184 setbits_le32(&reset_manager_base->per0modrst, eccmask); in socfpga_emac_manage_reset()
185 setbits_le32(&reset_manager_base->per0modrst, emacmask); in socfpga_emac_manage_reset()
219 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc); in socfpga_reset_deassert_bridges_handoff()
244 setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK); in socfpga_reset_assert_fpga_connected_peripherals()
245 setbits_le32(&reset_manager_base->per1modrst, mask1); in socfpga_reset_assert_fpga_connected_peripherals()
246 setbits_le32(&reset_manager_base->per0modrst, mask0); in socfpga_reset_assert_fpga_connected_peripherals()
286 setbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
314 setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp); in socfpga_per_reset_all()
317 setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp); in socfpga_per_reset_all()
[all …]
H A Dfreeze_controller.c132 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
141 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
147 setbits_le32(ioctrl_reg_offset, in sys_mgr_frzctrl_thaw_req()
163 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
193 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
206 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dpower.c47 setbits_le32(&power->usbhost_phy_control, in exynos5_set_usbhost_phy_ctrl()
63 setbits_le32(&power->usbhost_phy_control, in exynos4412_set_usbhost_phy_ctrl()
65 setbits_le32(&power->hsic1_phy_control, in exynos4412_set_usbhost_phy_ctrl()
67 setbits_le32(&power->hsic2_phy_control, in exynos4412_set_usbhost_phy_ctrl()
96 setbits_le32(&power->usbdrd_phy_control, in exynos5_set_usbdrd_phy_ctrl()
112 setbits_le32(&power->usbdev_phy_control, in exynos5420_set_usbdev_phy_ctrl()
114 setbits_le32(&power->usbdev1_phy_control, in exynos5420_set_usbdev_phy_ctrl()
162 setbits_le32(&power->ps_hold_control, in exynos5_set_ps_hold_ctrl()
203 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP); in set_hw_thermal_trip()
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c401 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, in enable_basic_clocks()
405 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, in enable_basic_clocks()
407 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, in enable_basic_clocks()
411 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, in enable_basic_clocks()
413 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, in enable_basic_clocks()
417 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, in enable_basic_clocks()
426 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); in enable_basic_clocks()
431 setbits_le32((*prcm)->cm_l3init_sata_clkctrl, in enable_basic_clocks()
436 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, in enable_basic_clocks()
438 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, in enable_basic_clocks()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_power_init.c64 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, in mxs_power_clock2pll()
72 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, in mxs_power_clock2pll()
105 setbits_le32(&rtc_regs->hw_rtc_persistent0, in mxs_power_set_auto_restart()
266 setbits_le32(&power_regs->hw_power_misc, in mxs_power_switch_dcdc_clocksource()
304 setbits_le32(&power_regs->hw_power_battmonitor, in mxs_src_power_init()
317 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); in mxs_src_power_init()
405 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
411 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
414 setbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_enable_4p2_dcdc_input()
453 setbits_le32(&power_regs->hw_power_ctrl, in mxs_enable_4p2_dcdc_input()
[all …]
/OK3568_Linux_fs/u-boot/drivers/fpga/
H A Dsocfpga_arria10.c50 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()
136 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cd_ratio()
235 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_reset()
286 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
296 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
319 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
344 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_init()
404 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
406 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_poll_usermode()
410 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun6i.c46 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
49 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
160 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
185 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
186 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
191 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
240 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); in mctl_channel_init()
245 setbits_le32(&mctl_ctl->ppcfg, 1); in mctl_channel_init()
278 setbits_le32(&mctl_com->dbgcr, (1 << 6)); in mctl_com_init()
282 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); in mctl_com_init()
[all …]
/OK3568_Linux_fs/u-boot/board/sunxi/
H A Dgmac.c17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); in eth_init_board()
18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); in eth_init_board()
20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); in eth_init_board()
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | in eth_init_board()
27 setbits_le32(&ccm->gmac_clk_cfg, in eth_init_board()
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | in eth_init_board()
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/
H A Dabb.c55 setbits_le32(setup, in abb_setup_timings()
107 setbits_le32(txdone, txdone_mask); in abb_setup()
110 setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); in abb_setup()
113 setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); in abb_setup()
120 setbits_le32(txdone, txdone_mask); in abb_setup()

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