105 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);  in sunxi_hdmi_hpd_detect()
107 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);  in sunxi_hdmi_hpd_detect()
110 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);  in sunxi_hdmi_hpd_detect()
144 	setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);  in sunxi_hdmi_ddc_do_command()
155 	setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);  in sunxi_hdmi_ddc_do_command()
225 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);  in sunxi_hdmi_edid_get_mode()
349 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0);  in sunxi_frontend_init()
350 	setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0);  in sunxi_frontend_init()
353 	setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN);  in sunxi_frontend_init()
364 	setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY);  in sunxi_frontend_init()
373 	setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);  in sunxi_frontend_mode_set()
393 	setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_REG_RDY);  in sunxi_frontend_mode_set()
401 	setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_FRM_START);  in sunxi_frontend_enable()
445 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);  in sunxi_composer_init()
449 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);  in sunxi_composer_init()
451 	setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);  in sunxi_composer_init()
459 	setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);  in sunxi_composer_init()
490 	setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);  in sunxi_composer_mode_set()
492 		setbits_le32(&de_be->mode,  in sunxi_composer_mode_set()
514 	setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);  in sunxi_composer_enable()
515 	setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);  in sunxi_composer_enable()
623 			setbits_le32(&ccm->lcd0_ch1_clk_cfg,  in sunxi_lcdc_pll_set()
640 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);  in sunxi_lcdc_init()
642 	setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);  in sunxi_lcdc_init()
646 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);  in sunxi_lcdc_init()
649 	setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS);  in sunxi_lcdc_init()
651 	setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);  in sunxi_lcdc_init()
851 	setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
881 		setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
900 		setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
903 		setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
912 	setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
927 	setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
929 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
965 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
967 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);