1*4882a593Smuzhiyun #include <common.h>
2*4882a593Smuzhiyun #include <netdev.h>
3*4882a593Smuzhiyun #include <miiphy.h>
4*4882a593Smuzhiyun #include <asm/gpio.h>
5*4882a593Smuzhiyun #include <asm/io.h>
6*4882a593Smuzhiyun #include <asm/arch/clock.h>
7*4882a593Smuzhiyun #include <asm/arch/gpio.h>
8*4882a593Smuzhiyun
eth_init_board(void)9*4882a593Smuzhiyun void eth_init_board(void)
10*4882a593Smuzhiyun {
11*4882a593Smuzhiyun int pin;
12*4882a593Smuzhiyun struct sunxi_ccm_reg *const ccm =
13*4882a593Smuzhiyun (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Set up clock gating */
16*4882a593Smuzhiyun #ifdef CONFIG_SUNXI_GEN_SUN6I
17*4882a593Smuzhiyun setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
18*4882a593Smuzhiyun setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
19*4882a593Smuzhiyun #else
20*4882a593Smuzhiyun setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Set MII clock */
24*4882a593Smuzhiyun #ifdef CONFIG_RGMII
25*4882a593Smuzhiyun setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
26*4882a593Smuzhiyun CCM_GMAC_CTRL_GPIT_RGMII);
27*4882a593Smuzhiyun setbits_le32(&ccm->gmac_clk_cfg,
28*4882a593Smuzhiyun CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
29*4882a593Smuzhiyun #else
30*4882a593Smuzhiyun setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
31*4882a593Smuzhiyun CCM_GMAC_CTRL_GPIT_MII);
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifndef CONFIG_MACH_SUN6I
35*4882a593Smuzhiyun /* Configure pin mux settings for GMAC */
36*4882a593Smuzhiyun for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
37*4882a593Smuzhiyun #ifdef CONFIG_RGMII
38*4882a593Smuzhiyun /* skip unused pins in RGMII mode */
39*4882a593Smuzhiyun if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
40*4882a593Smuzhiyun continue;
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
43*4882a593Smuzhiyun sunxi_gpio_set_drv(pin, 3);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun #elif defined CONFIG_RGMII
46*4882a593Smuzhiyun /* Configure sun6i RGMII mode pin mux settings */
47*4882a593Smuzhiyun for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
48*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
49*4882a593Smuzhiyun sunxi_gpio_set_drv(pin, 3);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
52*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
53*4882a593Smuzhiyun sunxi_gpio_set_drv(pin, 3);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
56*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
57*4882a593Smuzhiyun sunxi_gpio_set_drv(pin, 3);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
60*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
61*4882a593Smuzhiyun sunxi_gpio_set_drv(pin, 3);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun #elif defined CONFIG_GMII
64*4882a593Smuzhiyun /* Configure sun6i GMII mode pin mux settings */
65*4882a593Smuzhiyun for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
66*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
67*4882a593Smuzhiyun sunxi_gpio_set_drv(pin, 2);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun #else
70*4882a593Smuzhiyun /* Configure sun6i MII mode pin mux settings */
71*4882a593Smuzhiyun for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
72*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
73*4882a593Smuzhiyun for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
74*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
75*4882a593Smuzhiyun for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
76*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
77*4882a593Smuzhiyun for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
78*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
79*4882a593Smuzhiyun for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
80*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
81*4882a593Smuzhiyun #endif
82*4882a593Smuzhiyun }
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