Lines Matching refs:setbits_le32

119 	setbits_le32(&regs->cr, RCC_CR_HSION);  in configure_clocks()
128 	setbits_le32(&regs->cr, RCC_CR_HSEON);  in configure_clocks()
132 	setbits_le32(&regs->cfgr, ((  in configure_clocks()
147 	setbits_le32(&regs->cr, RCC_CR_PLLON);  in configure_clocks()
152 	setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);  in configure_clocks()
153 	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);  in configure_clocks()
158 	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);  in configure_clocks()
165 	setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);  in configure_clocks()
242 	setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));  in stm32_clk_enable()
251 		setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);  in clock_setup()
254 		setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);  in clock_setup()
257 		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);  in clock_setup()
258 		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);  in clock_setup()
259 		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);  in clock_setup()