Lines Matching refs:setbits_le32
46 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
49 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
160 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
185 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
186 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
191 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
240 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); in mctl_channel_init()
245 setbits_le32(&mctl_ctl->ppcfg, 1); in mctl_channel_init()
278 setbits_le32(&mctl_com->dbgcr, (1 << 6)); in mctl_com_init()
282 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); in mctl_com_init()
283 setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); in mctl_com_init()
289 setbits_le32(&prcm->vdd_sys_pwroff, in mctl_com_init()
302 setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); in mctl_port_cfg()
352 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in sunxi_dram_init()
356 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in sunxi_dram_init()
359 setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); in sunxi_dram_init()