230 	setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));  in pch_power_options()
259 	setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));  in cpt_pm_init()
261 	setbits_le32(RCB_REG(0x228c), 1 << 0);  in cpt_pm_init()
262 	setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));  in cpt_pm_init()
263 	setbits_le32(RCB_REG(0x0900), 1 << 14);  in cpt_pm_init()
265 	setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));  in cpt_pm_init()
266 	setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));  in cpt_pm_init()
270 	setbits_le32(RCB_REG(0x3340), 0xfffff);  in cpt_pm_init()
271 	setbits_le32(RCB_REG(0x3344), 1 << 1);  in cpt_pm_init()
289 	setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */  in cpt_pm_init()
290 	setbits_le32(RCB_REG(0x3a88), 1 << 0);  /* SATA 4/5 disabled */  in cpt_pm_init()
295 	setbits_le32(RCB_REG(0x21b0), 0xf);  in cpt_pm_init()
303 	setbits_le32(RCB_REG(0x2238), 1 << 0);  in ppt_pm_init()
304 	setbits_le32(RCB_REG(0x228c), 1 << 0);  in ppt_pm_init()
308 	setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));  in ppt_pm_init()
309 	setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));  in ppt_pm_init()
313 	setbits_le32(RCB_REG(0x3340), 0xfffff);  in ppt_pm_init()
314 	setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));  in ppt_pm_init()
332 	setbits_le32(RCB_REG(0x3a84), 1 << 24);  in ppt_pm_init()
334 	setbits_le32(RCB_REG(0x3a88), 1 << 0);  in ppt_pm_init()
338 	setbits_le32(RCB_REG(0x33a4), (1 << 0));  in ppt_pm_init()
340 	setbits_le32(RCB_REG(0x21b0), 0xf);  in ppt_pm_init()
354 	setbits_le32(RCB_REG(0x2234), 0xf);  in enable_clock_gating()
380 	setbits_le32(RCB_REG(0x38c0), 0x7);  in enable_clock_gating()
381 	setbits_le32(RCB_REG(0x36d4), 0x6680c004);  in enable_clock_gating()
382 	setbits_le32(RCB_REG(0x3564), 0x3);  in enable_clock_gating()
406 	setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));  in pch_fixups()
407 	setbits_le32(RCB_REG(0x21a8), 0x3);  in pch_fixups()
494 	setbits_le32(RCB_REG(GCS), 1 >> 5);	/* No reset */  in bd82x6x_lpc_early_init()