Lines Matching refs:setbits_le32
34 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
49 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
98 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
116 setbits_le32(&dv_pll1_regs->pllctl, in dm365_pll2_init()
131 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); in dm365_pll2_init()
175 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
191 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ); in dm365_ddr_setup()
198 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN); in dm365_ddr_setup()
201 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK); in dm365_ddr_setup()
207 setbits_le32(&dv_sys_module_regs->vtpiocr, in dm365_ddr_setup()
248 setbits_le32(&dv_sys_module_regs->vpss_clkctl, in dm365_vpss_sync_reset()
275 setbits_le32(TMPSTATUS, FLAG_PORRST); in dm365_por_reset()
290 setbits_le32(TMPSTATUS, FLAG_PORRST); in dm365_wdt_reset()
291 setbits_le32(TMPSTATUS, FLAG_FLGOFF); in dm365_wdt_reset()
310 setbits_le32(TMPSTATUS, FLAG_FLGON); in dm365_wdt_flag_on()
338 setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE); in dm365_psc_init()
367 setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND); in dm365_emif_init()
378 setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value)); in dm365_pinmux_ctl()