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Searched refs:sdhci_writel (Results 1 – 25 of 30) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-pci-dwc-mshc.c41 sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
49 sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
53 sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG); in sdhci_snps_set_clock()
54 sdhci_writel(host, CLKFBOUT_100_MHZ, in sdhci_snps_set_clock()
57 sdhci_writel(host, DIV_REG_200_MHZ, SDHC_MMCM_DIV_REG); in sdhci_snps_set_clock()
58 sdhci_writel(host, CLKFBOUT_200_MHZ, in sdhci_snps_set_clock()
65 sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
H A Dsdhci-milbeaut.c67 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
69 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
72 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
77 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
120 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
138 sdhci_writel(host, 0, MLB_SOFT_RESET); in sdhci_milbeaut_bridge_reset()
140 sdhci_writel(host, MLB_SOFT_RESET_RSTX, MLB_SOFT_RESET); in sdhci_milbeaut_bridge_reset()
169 sdhci_writel(host, val, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
171 sdhci_writel(host, MLB_CDR_SET_CLK2POW16, MLB_CDR_SET); in sdhci_milbeaut_bridge_init()
173 sdhci_writel(host, MLB_WP_CD_LED_SET_LED_INV, MLB_WP_CD_LED_SET); in sdhci_milbeaut_bridge_init()
[all …]
H A Dsdhci-of-esdhc.c522 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); in esdhc_of_adma_workaround()
545 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); in esdhc_of_enable_dma()
597 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); in esdhc_clock_enable()
625 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); in esdhc_flush_async_fifo()
718 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); in esdhc_of_set_clock()
742 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); in esdhc_of_set_clock()
744 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); in esdhc_of_set_clock()
751 sdhci_writel(host, temp, ESDHC_DLLCFG0); in esdhc_of_set_clock()
754 sdhci_writel(host, temp, ESDHC_DLLCFG0); in esdhc_of_set_clock()
757 sdhci_writel(host, temp, ESDHC_DLLCFG0); in esdhc_of_set_clock()
[all …]
H A Dsdhci-of-dwcmshc.c229 sdhci_writel(host, vendor, reg); in dwcmshc_hs400_enhanced_strobe()
275 sdhci_writel(host, extra, reg); in dwcmshc_rk3568_set_clock()
282 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
287 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
288 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); in dwcmshc_rk3568_set_clock()
289 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); in dwcmshc_rk3568_set_clock()
290 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); in dwcmshc_rk3568_set_clock()
299 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); in dwcmshc_rk3568_set_clock()
304 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
306 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
[all …]
H A Dsdhci-xenon-phy.c237 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_init()
353 sdhci_writel(host, reg, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
408 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); in xenon_emmc_phy_config_tuning()
422 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
428 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_disable_strobe()
432 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_disable_strobe()
465 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
472 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_strobe_delay_adj()
477 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_strobe_delay_adj()
536 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_slow_mode()
[all …]
H A Dsdhci_f_sdh30.c37 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
39 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
42 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
49 sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
54 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
75 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
163 sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
165 sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
H A Dsdhci-xenon.c31 sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
65 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
78 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_set_acg()
89 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
107 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
118 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
128 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
140 sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL); in xenon_retune_setup()
145 sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
148 sdhci_writel(host, reg, SDHCI_INT_ENABLE); in xenon_retune_setup()
[all …]
H A Dsdhci-pci-gli.c127 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); in gl9750_wt_on()
144 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); in gl9750_wt_off()
174 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); in gli_set_9750()
179 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); in gli_set_9750()
210 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()
211 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); in gli_set_9750()
222 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
225 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); in gli_set_9750()
231 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
256 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv()
[all …]
H A Dsdhci-bcm-kona.c69 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
89 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
101 sdhci_writel(host, val, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
114 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
149 sdhci_writel(host, val, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
152 sdhci_writel(host, val, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
H A Dsdhci-sprd.c111 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
188 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
233 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
243 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
250 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
256 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
348 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); in sdhci_sprd_set_uhs_signaling()
517 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], in sdhci_sprd_hs400_enhanced_strobe()
H A Dsdhci-tegra.c348 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
400 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); in tegra_sdhci_reset()
401 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
407 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_reset()
430 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
444 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
490 sdhci_writel(host, reg, in tegra_sdhci_set_padctrl()
552 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
570 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
801 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); in tegra_sdhci_hs400_enhanced_strobe()
[all …]
H A Dsdhci.c175 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_set_card_detection()
176 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_set_card_detection()
272 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_set_default_irqs()
273 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_set_default_irqs()
571 sdhci_writel(host, scratch, SDHCI_BUFFER); in sdhci_write_block_pio()
846 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS); in sdhci_set_adma_addr()
848 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI); in sdhci_set_adma_addr()
864 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); in sdhci_set_sdma_addr()
1005 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_set_transfer_irqs()
1006 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_set_transfer_irqs()
[all …]
H A Dsdhci-pci-o2micro.c108 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
111 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
115 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
142 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
255 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
625 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
H A Dsdhci-sirf.c91 sdhci_writel(host, in sdhci_sirf_execute_tuning()
125 sdhci_writel(host, in sdhci_sirf_execute_tuning()
H A Dsdhci-of-arasan.c354 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
795 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
798 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
861 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
863 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
866 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
868 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
H A Dsdhci-omap.c467 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_omap_execute_tuning()
468 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_execute_tuning()
494 sdhci_writel(host, ier, SDHCI_INT_ENABLE); in sdhci_omap_card_busy()
495 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_card_busy()
510 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_omap_card_busy()
511 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_card_busy()
855 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS); in sdhci_omap_irq()
H A Dsdhci-acpi.c476 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG); in sdhci_acpi_qcom_handler()
477 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG); in sdhci_acpi_qcom_handler()
560 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER); in sdhci_acpi_amd_hs400_dll()
563 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER); in sdhci_acpi_amd_hs400_dll()
H A Dsdhci-esdhc-mcf.c201 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_mcf_reset()
202 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_mcf_reset()
H A Dsdhci.h665 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
715 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dxenon_sdhci.c136 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
157 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
207 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
213 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
228 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
246 sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
267 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
279 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
289 sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
299 sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL); in xenon_mmc_disable_tuning()
[all …]
H A Drockchip_sdhci.c343 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
345 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
350 sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL); in dwcmshc_sdhci_emmc_set_clock()
356 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
374 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); in dwcmshc_sdhci_emmc_set_clock()
389 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); in dwcmshc_sdhci_emmc_set_clock()
398 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); in dwcmshc_sdhci_emmc_set_clock()
405 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); in dwcmshc_sdhci_emmc_set_clock()
408 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
413 sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3); in dwcmshc_sdhci_emmc_set_clock()
[all …]
H A Dkona_sdhci.c35 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
52 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
56 sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
59 sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); in init_kona_mmc_core()
63 sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
H A Dsdhci.c67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); in sdhci_transfer_pio()
96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); in sdhci_transfer_data()
110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); in sdhci_transfer_data()
113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); in sdhci_transfer_data()
177 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
188 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
251 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
263 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
290 sdhci_writel(host, mask, SDHCI_INT_STATUS);
301 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
[all …]
H A Ds5p_sdhci.c40 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); in s5p_sdhci_set_control_reg()
50 sdhci_writel(host, val, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
62 sdhci_writel(host, val, SDHCI_CONTROL3); in s5p_sdhci_set_control_reg()
73 sdhci_writel(host, ctrl, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
/OK3568_Linux_fs/u-boot/include/
H A Dsdhci.h300 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
350 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function

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