| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
39 - reg : offsets for the register set for controlling the DPLL.
49 - DPLL mode setting - defining any one or more of the following overrides
51 - ti,low-power-stop : DPLL supports low power stop mode, gating output
52 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
53 - ti,lock : DPLL locks in programmed rate
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| H A D | apll.txt | 11 a subtype of a DPLL [2], although a simplified one at that.
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
186 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_pll_rate()
187 priv->cru, DPLL); in rk3308_clk_get_pll_rate()
275 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
276 priv->cru, DPLL); in rk3308_mac_set_clk()
943 rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_rate()
944 priv->cru, DPLL); in rk3308_clk_get_rate()
1024 ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru, in rk3308_clk_set_rate()
1025 DPLL, rate); in rk3308_clk_set_rate()
1026 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_set_rate()
[all …]
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| H A D | clk_rk322x.c | 84 [DPLL] = PLL(pll_rk3036, PLL_DPLL, RK2928_PLL_CON(3),
674 ret = rockchip_pll_set_rate(&rk322x_pll_clks[DPLL], in rk322x_clk_set_rate()
675 priv->cru, DPLL, rate); in rk322x_clk_set_rate()
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| H A D | clk_rv1106.c | 41 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1106_PLL_CON(16),
1056 rate = rockchip_pll_get_rate(&rv1106_pll_clks[DPLL], priv->cru, in rv1106_clk_get_rate()
1057 DPLL); in rv1106_clk_get_rate()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 20 #define DPLL 9 macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/ |
| H A D | intel_dvo.c | 494 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
495 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init()
503 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
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| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | exynos5422-odroid-core.dtsi | 97 /* derived from 600MHz DPLL */
199 /* derived from 600MHz DPLL */
235 /* derived from 600MHz DPLL */
247 /* derived from 600MHz DPLL */
262 /* derived from 600MHz DPLL */
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| /OK3568_Linux_fs/kernel/arch/arm/mach-omap2/ |
| H A D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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| /OK3568_Linux_fs/u-boot/board/rockchip/evb_rv1108/ |
| H A D | README | 31 APLL: 400000000 DPLL:798000000 GPLL:384000000
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 16 DPLL, enumerator
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| H A D | cru_rk3128.h | 64 DPLL, enumerator
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| H A D | cru_rk322x.h | 61 DPLL, enumerator
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| H A D | cru_rk3328.h | 59 DPLL, enumerator
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| H A D | cru_rv1106.h | 27 DPLL, enumerator
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| H A D | cru_rk1808.h | 21 DPLL, enumerator
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| H A D | cru_rk3528.h | 26 DPLL, enumerator
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| H A D | cru_rv1126.h | 49 DPLL, enumerator
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| H A D | cru_px30.h | 28 DPLL, enumerator
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| H A D | cru_rk3562.h | 29 DPLL, enumerator
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| H A D | cru_rk3568.h | 22 DPLL, enumerator
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| H A D | cru_rk3308.h | 36 DPLL, enumerator
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| /OK3568_Linux_fs/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3308.c | 202 pll_set(DPLL, priv, &rk3308_pll_div); in rkdclk_init()
270 pll_set(DPLL, priv, &rk3308_pll_div); in rkdclk_init()
333 pll_set(DPLL, priv, &rk3308_pll_div); in rkdclk_init()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/ |
| H A D | ti-phy.txt | 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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