1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3308_H 7 #define _ASM_ARCH_CRU_RK3308_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (816 * MHz) 15 16 #define CORE_ACLK_HZ 408000000 17 #define CORE_DBG_HZ 204000000 18 19 #define BUS_ACLK_HZ 200000000 20 #define BUS_HCLK_HZ 100000000 21 #define BUS_PCLK_HZ 100000000 22 23 #define PERI_ACLK_HZ 200000000 24 #define PERI_HCLK_HZ 100000000 25 #define PERI_PCLK_HZ 100000000 26 27 #define AUDIO_HCLK_HZ 100000000 28 #define AUDIO_PCLK_HZ 100000000 29 30 #define RK3308_PLL_CON(x) ((x) * 0x4) 31 #define RK3308_MODE_CON 0xa0 32 33 /* RK3308 pll id */ 34 enum rk3308_pll_id { 35 APLL, 36 DPLL, 37 VPLL0, 38 VPLL1, 39 PLL_COUNT, 40 }; 41 42 struct rk3308_clk_info { 43 unsigned long id; 44 char *name; 45 }; 46 47 /* Private data for the clock driver - used by rockchip_get_cru() */ 48 struct rk3308_clk_priv { 49 struct rk3308_cru *cru; 50 ulong armclk_hz; 51 ulong dpll_hz; 52 ulong vpll0_hz; 53 ulong vpll1_hz; 54 ulong armclk_enter_hz; 55 ulong armclk_init_hz; 56 bool sync_kernel; 57 bool set_armclk_rate; 58 }; 59 60 struct rk3308_cru { 61 struct rk3308_pll { 62 unsigned int con0; 63 unsigned int con1; 64 unsigned int con2; 65 unsigned int con3; 66 unsigned int con4; 67 unsigned int reserved0[3]; 68 } pll[4]; 69 unsigned int reserved1[8]; 70 unsigned int mode; 71 unsigned int misc; 72 unsigned int reserved2[2]; 73 unsigned int glb_cnt_th; 74 unsigned int glb_rst_st; 75 unsigned int glb_srst_fst; 76 unsigned int glb_srst_snd; 77 unsigned int glb_rst_con; 78 unsigned int pll_lock; 79 unsigned int reserved3[6]; 80 unsigned int hwffc_con0; 81 unsigned int reserved4; 82 unsigned int hwffc_th; 83 unsigned int hwffc_intst; 84 unsigned int apll_con0_s; 85 unsigned int apll_con1_s; 86 unsigned int clksel_con0_s; 87 unsigned int reserved5; 88 unsigned int clksel_con[74]; 89 unsigned int reserved6[54]; 90 unsigned int clkgate_con[15]; 91 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 92 unsigned int ssgtbl[32]; 93 unsigned int softrst_con[10]; 94 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 95 unsigned int sdmmc_con[2]; 96 unsigned int sdio_con[2]; 97 unsigned int emmc_con[2]; 98 }; 99 100 enum { 101 /* PLLCON0*/ 102 PLL_BP_SHIFT = 15, 103 PLL_POSTDIV1_SHIFT = 12, 104 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 105 PLL_FBDIV_SHIFT = 0, 106 PLL_FBDIV_MASK = 0xfff, 107 108 /* PLLCON1 */ 109 PLL_PDSEL_SHIFT = 15, 110 PLL_PD1_SHIFT = 14, 111 PLL_PD_SHIFT = 13, 112 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 113 PLLPD0_POWER_DOWN = 1, 114 PLLPD0_NO_POWER_DOWN = 0, 115 PLL_DSMPD_SHIFT = 12, 116 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 117 PLL_LOCK_STATUS_SHIFT = 10, 118 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 119 PLL_POSTDIV2_SHIFT = 6, 120 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 121 PLL_REFDIV_SHIFT = 0, 122 PLL_REFDIV_MASK = 0x3f, 123 124 /* PLLCON2 */ 125 PLL_FOUT4PHASEPD_SHIFT = 27, 126 PLL_FOUTVCOPD_SHIFT = 26, 127 PLL_FOUTPOSTDIVPD_SHIFT = 25, 128 PLL_DACPD_SHIFT = 24, 129 PLL_FRAC_DIV = 0xffffff, 130 131 /* CRU_MODE */ 132 PLLMUX_FROM_XIN24M = 0, 133 PLLMUX_FROM_PLL, 134 PLLMUX_FROM_RTC32K, 135 USBPHY480M_MODE_SHIFT = 8, 136 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 137 VPLL1_MODE_SHIFT = 6, 138 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 139 VPLL0_MODE_SHIFT = 4, 140 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 141 DPLL_MODE_SHIFT = 2, 142 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 143 APLL_MODE_SHIFT = 0, 144 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 145 146 /* CRU_CLK_SEL0_CON */ 147 CORE_ACLK_DIV_SHIFT = 12, 148 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 149 CORE_DBG_DIV_SHIFT = 8, 150 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 151 CORE_CLK_PLL_SEL_SHIFT = 6, 152 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 153 CORE_CLK_PLL_SEL_APLL = 0, 154 CORE_CLK_PLL_SEL_VPLL0, 155 CORE_CLK_PLL_SEL_VPLL1, 156 CORE_DIV_CON_SHIFT = 0, 157 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 158 159 /* CRU_CLK_SEL2_CON */ 160 CLK_RTC32K_SEL_SHIFT = 8, 161 CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT, 162 CLK_RTC32K_IO = 0, 163 CLK_RTC32K_PVTM, 164 CLK_RTC32K_FRAC_DIV, 165 CLK_RTC32K_DIV, 166 167 /* CRU_CLK_SEL3_CON */ 168 CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, 169 CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 170 CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 171 CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 172 173 /* CRU_CLK_SEL5_CON */ 174 BUS_PLL_SEL_SHIFT = 6, 175 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 176 BUS_PLL_SEL_DPLL = 0, 177 BUS_PLL_SEL_VPLL0, 178 BUS_PLL_SEL_VPLL1, 179 BUS_ACLK_DIV_SHIFT = 0, 180 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 181 182 /* CRU_CLK_SEL6_CON */ 183 BUS_PCLK_DIV_SHIFT = 8, 184 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 185 BUS_HCLK_DIV_SHIFT = 0, 186 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 187 188 /* CRU_CLK_SEL7_CON */ 189 CRYPTO_APK_SEL_SHIFT = 14, 190 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, 191 CRYPTO_PLL_SEL_DPLL = 0, 192 CRYPTO_PLL_SEL_VPLL0, 193 CRYPTO_PLL_SEL_VPLL1 = 0, 194 CRYPTO_APK_DIV_SHIFT = 8, 195 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 196 CRYPTO_PLL_SEL_SHIFT = 6, 197 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, 198 CRYPTO_DIV_SHIFT = 0, 199 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 200 201 /* CRU_CLK_SEL8_CON */ 202 DCLK_VOP_SEL_SHIFT = 14, 203 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 204 DCLK_VOP_SEL_DIVOUT = 0, 205 DCLK_VOP_SEL_FRACOUT, 206 DCLK_VOP_SEL_24M, 207 DCLK_VOP_PLL_SEL_SHIFT = 10, 208 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 209 DCLK_VOP_PLL_SEL_DPLL = 0, 210 DCLK_VOP_PLL_SEL_VPLL0, 211 DCLK_VOP_PLL_SEL_VPLL1, 212 DCLK_VOP_DIV_SHIFT = 0, 213 DCLK_VOP_DIV_MASK = 0xff, 214 215 /* CRU_CLK_SEL25_CON */ 216 /* CRU_CLK_SEL26_CON */ 217 /* CRU_CLK_SEL27_CON */ 218 /* CRU_CLK_SEL28_CON */ 219 CLK_I2C_PLL_SEL_SHIFT = 14, 220 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 221 CLK_I2C_PLL_SEL_DPLL = 0, 222 CLK_I2C_PLL_SEL_VPLL0, 223 CLK_I2C_PLL_SEL_24M, 224 CLK_I2C_DIV_CON_SHIFT = 0, 225 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 226 227 /* CRU_CLK_SEL29_CON */ 228 CLK_PWM_PLL_SEL_SHIFT = 14, 229 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 230 CLK_PWM_PLL_SEL_DPLL = 0, 231 CLK_PWM_PLL_SEL_VPLL0, 232 CLK_PWM_PLL_SEL_24M, 233 CLK_PWM_DIV_CON_SHIFT = 0, 234 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 235 236 /* CRU_CLK_SEL30_CON */ 237 /* CRU_CLK_SEL31_CON */ 238 /* CRU_CLK_SEL32_CON */ 239 CLK_SPI_PLL_SEL_SHIFT = 14, 240 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 241 CLK_SPI_PLL_SEL_DPLL = 0, 242 CLK_SPI_PLL_SEL_VPLL0, 243 CLK_SPI_PLL_SEL_24M, 244 CLK_SPI_DIV_CON_SHIFT = 0, 245 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 246 247 /* CRU_CLK_SEL34_CON */ 248 CLK_SARADC_DIV_CON_SHIFT = 0, 249 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 250 251 /* CRU_CLK_SEL36_CON */ 252 PERI_PLL_SEL_SHIFT = 6, 253 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 254 PERI_PLL_DPLL = 0, 255 PERI_PLL_VPLL0, 256 PERI_PLL_VPLL1, 257 PERI_ACLK_DIV_SHIFT = 0, 258 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 259 260 /* CRU_CLK_SEL37_CON */ 261 PERI_PCLK_DIV_SHIFT = 8, 262 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 263 PERI_HCLK_DIV_SHIFT = 0, 264 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 265 266 /* CRU_CLKSEL41_CON */ 267 EMMC_CLK_SEL_SHIFT = 15, 268 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 269 EMMC_CLK_SEL_EMMC = 0, 270 EMMC_CLK_SEL_EMMC_DIV50, 271 EMMC_PLL_SHIFT = 8, 272 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 273 EMMC_SEL_DPLL = 0, 274 EMMC_SEL_VPLL0, 275 EMMC_SEL_VPLL1, 276 EMMC_SEL_24M, 277 EMMC_DIV_SHIFT = 0, 278 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 279 280 /* CRU_CLKSEL42_CON */ 281 SCLK_SFC_SEL_SHIFT = 14, 282 SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, 283 SCLK_SFC_SEL_DPLL = 0, 284 SCLK_SFC_SEL_VPLL0, 285 SCLK_SFC_SEL_VPLL1, 286 SCLK_SFC_DIV_SHIFT = 0, 287 SCLK_SFC_DIV_MASK = 0x7f << SCLK_SFC_DIV_SHIFT, 288 289 /* CRU_CLKSEL43_CON */ 290 MAC_CLK_SPEED_SEL_SHIFT = 15, 291 MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT, 292 MAC_CLK_SPEED_SEL_10M = 0, 293 MAC_CLK_SPEED_SEL_100M, 294 MAC_CLK_SOURCE_SEL_SHIFT = 14, 295 MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT, 296 MAC_CLK_SOURCE_SEL_INTERNAL = 0, 297 MAC_CLK_SOURCE_SEL_EXTERNAL, 298 MAC_PLL_SHIFT = 6, 299 MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT, 300 MAC_SEL_DPLL = 0, 301 MAC_SEL_VPLL0, 302 MAC_SEL_VPLL1, 303 MAC_DIV_SHIFT = 0, 304 MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT, 305 306 /* CRU_CLK_SEL45_CON */ 307 AUDIO_PCLK_DIV_SHIFT = 8, 308 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, 309 AUDIO_PLL_SEL_SHIFT = 6, 310 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, 311 AUDIO_PLL_VPLL0 = 0, 312 AUDIO_PLL_VPLL1, 313 AUDIO_PLL_24M, 314 AUDIO_HCLK_DIV_SHIFT = 0, 315 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, 316 }; 317 318 check_member(rk3308_cru, emmc_con[1], 0x494); 319 320 enum { /* DPLL_CON0, VPLL0_CON0, VPLL1_CON0 */ 321 POSTDIV1_SHIFT = 12, 322 POSTDIV1_MASK = 0x7 << POSTDIV1_SHIFT, 323 FBDIV_SHIFT = 0, 324 FBDIV_MASK = 0xfff << FBDIV_SHIFT, 325 326 /* DPLL_CON1, VPLL0_CON1, VPLL1_CON1 */ 327 PLLPD0_SHIFT = 13, 328 PLLPD0_MASK = 1 << PLLPD0_SHIFT, 329 DSMPD_SHIFT = 12, 330 DSMPD_MASK = 1 << DSMPD_SHIFT, 331 INTEGER_MODE = 1, 332 FRACTIONAL_MODE = 0, 333 PLL_LOCK_SHIFT = 10, 334 PLL_LOCK_MASK = 0x1 << PLL_LOCK_SHIFT, 335 POSTDIV2_SHIFT = 6, 336 POSTDIV2_MASK = 0x7 << POSTDIV2_SHIFT, 337 REFDIV_SHIFT = 0, 338 REFDIV_MASK = 0x3f << REFDIV_SHIFT, 339 340 /* VPLL0_CON2, VPLL1_CON2 */ 341 FRACDIV_SHIFT = 0, 342 FRACDIV_MASK = 0xffffff << FRACDIV_SHIFT, 343 344 /* CRU_MODE */ 345 VPLL1_CLK_SEL_SHIFT = 13, 346 VPLL1_CLK_SEL_MASK = 0x1 << VPLL1_CLK_SEL_SHIFT, 347 VPLL1_CLK_SEL_WITHOUT_LVL_SHIFT = 1, 348 349 VPLL0_CLK_SEL_SHIFT = 12, 350 VPLL0_CLK_SEL_MASK = 0x1 << VPLL0_CLK_SEL_SHIFT, 351 VPLL0_CLK_SEL_WITHOUT_LVL_SHIFT = 1, 352 353 DPLL_CLK_SEL_SHIFT = 11, 354 DPLL_CLK_SEL_MASK = 0x1 << DPLL_CLK_SEL_SHIFT, 355 DPLL_CLK_SEL_WITHOUT_LVL_SHIFT = 1, 356 357 APLL_CLK_SEL_SHIFT = 10, 358 APLL_CLK_SEL_MASK = 0x1 << APLL_CLK_SEL_SHIFT, 359 APLL_CLK_SEL_WITHOUT_LVL_SHIFT = 1, 360 361 VPLL1_WORK_MODE_SHIFT = 6, 362 VPLL1_WORK_MODE_MASK = 0x3 << VPLL1_WORK_MODE_SHIFT, 363 VPLL1_WORK_MODE_XIN_OSC0 = 0, 364 VPLL1_WORK_MODE_PLL = 1, 365 VPLL1_WORK_MODE_32K = 2, 366 367 VPLL0_WORK_MODE_SHIFT = 4, 368 VPLL0_WORK_MODE_MASK = 0x3 << VPLL0_WORK_MODE_SHIFT, 369 VPLL0_WORK_MODE_XIN_OSC0 = 0, 370 VPLL0_WORK_MODE_PLL = 1, 371 VPLL0_WORK_MODE_32K = 2, 372 373 DPLL_WORK_MODE_SHIFT = 2, 374 DPLL_WORK_MODE_MASK = 0x3 << DPLL_WORK_MODE_SHIFT, 375 DPLL_WORK_MODE_XIN_OSC0 = 0, 376 DPLL_WORK_MODE_PLL = 1, 377 DPLL_WORK_MODE_32K = 2, 378 379 APLL_WORK_MODE_SHIFT = 0, 380 APLL_WORK_MODE_MASK = 0x3 << APLL_WORK_MODE_SHIFT, 381 APLL_WORK_MODE_XIN_OSC0 = 0, 382 APLL_WORK_MODE_PLL = 1, 383 384 /* GLB_RST_CON */ 385 WDT_GLB_SRST_CTRL_SHIFT = 1, 386 WDT_GLB_SRST_CTRL = 1, 387 TSADC_GLB_SRST_CTRL_SHIFT = 0, 388 TSADC_GLB_SRST_CTRL = 1, 389 390 /* CLKSEL_CON1 */ 391 DDRPHY4X_PLL_CLK_SEL_SHIFT = 6, 392 DDRPHY4X_PLL_CLK_SEL_MASK = 0x3 << DDRPHY4X_PLL_CLK_SEL_SHIFT, 393 DDRPHY4X_PLL_CLK_SEL_DPLL = 0, 394 DDRPHY4X_DIV_CON_SIHFT = 0, 395 DDRPHY4X_DIV_CON_MASK = 0x7 << DDRPHY4X_DIV_CON_SIHFT, 396 DDRPHY4X_DIV_CON = 0, 397 398 /* CLKSEL_CON5 */ 399 A_H_PCLK_BUS_PLL_SEL_SHIFT = 6, 400 A_H_PCLK_BUS_PLL_SEL_MASK = 0x3 << A_H_PCLK_BUS_PLL_SEL_SHIFT, 401 A_H_PCLK_BUS_PLL_SEL_DPLL = 0, 402 A_H_PCLK_BUS_PLL_SEL_VPLL0 = 1, 403 A_H_PCLK_BUS_PLL_SEL_VPLL1 = 2, 404 ACLK_BUS_DIV_CON_SHIFT = 0, 405 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 406 ACLK_BUS_DIV_CON_7 = 7, 407 ACLK_BUS_DIV_CON_5 = 5, 408 ACLK_BUS_DIV_CON_3 = 3, 409 410 /* CLKSEL_CON6 */ 411 PCLK_BUS_DIV_CON_SHIFT = 8, 412 PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, 413 PCLK_BUS_DIV_CON_31 = 31, 414 PCLK_BUS_DIV_CON_25 = 25, 415 PCLK_BUS_DIV_CON_15 = 15, 416 HCLK_BUS_DIV_CON_SHIFT = 0, 417 HCLK_BUS_DIV_CON_MASK = 0x1f << HCLK_BUS_DIV_CON_SHIFT, 418 HCLK_BUS_DIV_CON_15 = 15, 419 HCLK_BUS_DIV_CON_13 = 13, 420 HCLK_BUS_DIV_CON_11 = 11, 421 HCLK_BUS_DIV_CON_7 = 7, 422 423 /* CLKSEL_CON7 */ 424 CLK_CRYPTO_APK_SEL_SHIFT = 14, 425 CLK_CRYPTO_APK_SEL_MASK = 0x3 << CLK_CRYPTO_APK_SEL_SHIFT, 426 CLK_CRYPTO_APK_SEL_DPLL = 0, 427 CLK_CRYPTO_APK_DIV_SHIFT = 8, 428 CLK_CRYPTO_APK_DIV_MASK = 0x1f << CLK_CRYPTO_APK_DIV_SHIFT, 429 CLK_CRYPTO_APK_DIV_15 = 15, 430 CLK_CRYPTO_APK_DIV_13 = 13, 431 CLK_CRYPTO_APK_DIV_11 = 11, 432 CLK_CRYPTO_APK_DIV_7 = 7, 433 CLK_CRYPTO_PLL_SEL_SHIFT = 6, 434 CLK_CRYPTO_PLL_SEL_MASK = 0x3 << CLK_CRYPTO_PLL_SEL_SHIFT, 435 CLK_CRYPTO_PLL_SEL_DPLL = 0, 436 CLK_CRYPTO_DIV_CON_SHIFT = 0, 437 CLK_CRYPTO_DIV_CON_MASK = 0x1f << CLK_CRYPTO_DIV_CON_SHIFT, 438 CLK_CRYPTO_DIV_CON_15 = 15, 439 CLK_CRYPTO_DIV_CON_13 = 13, 440 CLK_CRYPTO_DIV_CON_11 = 11, 441 CLK_CRYPTO_DIV_CON_7 = 7, 442 443 /* CLKSEL_CON8 */ 444 DCLK_VOP_SEL_DCLK_VOP = 0, 445 DCLK_VOP_DIV_CON_SHIFT = 0, 446 DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, 447 DCLK_VOP_DIV_CON_15 = 15, 448 DCLK_VOP_DIV_CON_11 = 11, 449 450 /* CLKSEL_CON10 */ 451 CLK_UART0_PLL_SEL_SHIFT = 13, 452 CLK_UART0_PLL_SEL_MASK = 0x7 << CLK_UART0_PLL_SEL_SHIFT, 453 CLK_UART0_PLL_SEL_XIN_OSC0 = 4, 454 CLK_UART0_DIV_CON_SHIFT = 0, 455 CLK_UART0_DIV_CON_MASK = 0x1f << CLK_UART0_DIV_CON_SHIFT, 456 CLK_UART0_DIV_CON = 0, 457 CLK_UART0_DIV_CON_15 = 15, 458 459 /* CLKSEL_CON13 */ 460 CLK_UART1_PLL_SEL_SHIFT = 13, 461 CLK_UART1_PLL_SEL_MASK = 0x7 << CLK_UART1_PLL_SEL_SHIFT, 462 CLK_UART1_PLL_SEL_XIN_OSC0 = 4, 463 CLK_UART1_DIV_CON_SHIFT = 0, 464 CLK_UART1_DIV_CON_MASK = 0x1f << CLK_UART1_DIV_CON_SHIFT, 465 CLK_UART1_DIV_CON = 0, 466 CLK_UART1_DIV_CON_15 = 15, 467 468 /* CLKSEL_CON16 */ 469 CLK_UART2_PLL_SEL_SHIFT = 13, 470 CLK_UART2_PLL_SEL_MASK = 0x7 << CLK_UART2_PLL_SEL_SHIFT, 471 CLK_UART2_PLL_SEL_XIN_OSC0 = 4, 472 CLK_UART2_DIV_CON_SHIFT = 0, 473 CLK_UART2_DIV_CON_MASK = 0x1f << CLK_UART2_DIV_CON_SHIFT, 474 CLK_UART2_DIV_CON = 0, 475 CLK_UART2_DIV_CON_15 = 15, 476 477 /* CLKSEL_CON19 */ 478 CLK_UART3_PLL_SEL_SHIFT = 13, 479 CLK_UART3_PLL_SEL_MASK = 0x7 << CLK_UART3_PLL_SEL_SHIFT, 480 CLK_UART3_PLL_SEL_XIN_OSC0 = 4, 481 CLK_UART3_DIV_CON_SHIFT = 0, 482 CLK_UART3_DIV_CON_MASK = 0x1f << CLK_UART3_DIV_CON_SHIFT, 483 CLK_UART3_DIV_CON = 0, 484 CLK_UART3_DIV_CON_15 = 15, 485 486 /* CLKSEL_CON22 */ 487 CLK_UART4_PLL_SEL_SHIFT = 13, 488 CLK_UART4_PLL_SEL_MASK = 0x7 << CLK_UART4_PLL_SEL_SHIFT, 489 CLK_UART4_PLL_SEL_XIN_OSC0 = 4, 490 CLK_UART4_DIV_CON_SHIFT = 0, 491 CLK_UART4_DIV_CON_MASK = 0x1f << CLK_UART4_DIV_CON_SHIFT, 492 CLK_UART4_DIV_CON = 0, 493 CLK_UART4_DIV_CON_15 = 15, 494 495 /* CLKSEL_CON25 */ 496 CLK_I2C0_PLL_SEL_SHIFT = 14, 497 CLK_I2C0_PLL_SEL_MASK = 0x3 << CLK_I2C0_PLL_SEL_SHIFT, 498 CLK_I2C0_PLL_SEL_DPLL = 0, 499 CLK_I2C0_DIV_CON_SHIFT = 0, 500 CLK_I2C0_DIV_CON_MASK = 0x7f << CLK_I2C0_DIV_CON_SHIFT, 501 CLK_I2C0_DIV_CON_7 = 7, 502 CLK_I2C0_DIV_CON_5 = 5, 503 CLK_I2C0_DIV_CON_3 = 3, 504 505 /* CLKSEL_CON26 */ 506 CLK_I2C1_PLL_SEL_SHIFT = 14, 507 CLK_I2C1_PLL_SEL_MASK = 0x3 << CLK_I2C1_PLL_SEL_SHIFT, 508 CLK_I2C1_PLL_SEL_DPLL = 0, 509 CLK_I2C1_DIV_CON_SHIFT = 0, 510 CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, 511 CLK_I2C1_DIV_CON_7 = 7, 512 CLK_I2C1_DIV_CON_5 = 5, 513 CLK_I2C1_DIV_CON_3 = 3, 514 515 /* CLKSEL_CON27 */ 516 CLK_I2C2_PLL_SEL_SHIFT = 14, 517 CLK_I2C2_PLL_SEL_MASK = 0x3 << CLK_I2C2_PLL_SEL_SHIFT, 518 CLK_I2C2_PLL_SEL_DPLL = 0, 519 CLK_I2C2_DIV_CON_SHIFT = 0, 520 CLK_I2C2_DIV_CON_MASK = 0x7f << CLK_I2C2_DIV_CON_SHIFT, 521 CLK_I2C2_DIV_CON_7 = 7, 522 CLK_I2C2_DIV_CON_5 = 5, 523 CLK_I2C2_DIV_CON_3 = 3, 524 525 /* CLKSEL_CON28 */ 526 CLK_I2C3_PLL_SEL_SHIFT = 14, 527 CLK_I2C3_PLL_SEL_MASK = 0x3 << CLK_I2C3_PLL_SEL_SHIFT, 528 CLK_I2C3_PLL_SEL_DPLL = 0, 529 CLK_I2C3_DIV_CON_SHIFT = 0, 530 CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, 531 CLK_I2C3_DIV_CON_7 = 7, 532 CLK_I2C3_DIV_CON_5 = 5, 533 CLK_I2C3_DIV_CON_3 = 3, 534 535 /* CLKSEL_CON29 */ 536 CLK_PWM_DIV_CON_15 = 15, 537 CLK_PWM_DIV_CON_11 = 11, 538 CLK_PWM_DIV_CON_7 = 7, 539 540 /* CLKSEL_CON30 */ 541 CLK_SPI0_PLL_SEL_SHIFT = 14, 542 CLK_SPI0_PLL_SEL_MASK = 0x3 << CLK_SPI0_PLL_SEL_SHIFT, 543 CLK_SPI0_PLL_SEL_DPLL = 0, 544 CLK_SPI0_DIV_CON_SHIFT = 0, 545 CLK_SPI0_DIV_CON_MASK = 0x7f << CLK_SPI0_DIV_CON_SHIFT, 546 CLK_SPI0_DIV_CON_15 = 15, 547 CLK_SPI0_DIV_CON_11 = 11, 548 CLK_SPI0_DIV_CON_7 = 7, 549 550 /* CLKSEL_CON31 */ 551 CLK_SPI1_PLL_SEL_SHIFT = 14, 552 CLK_SPI1_PLL_SEL_MASK = 0x3 << CLK_SPI1_PLL_SEL_SHIFT, 553 CLK_SPI1_PLL_SEL_DPLL = 0, 554 CLK_SPI1_DIV_CON_SHIFT = 0, 555 CLK_SPI1_DIV_CON_MASK = 0x7f << CLK_SPI1_DIV_CON_SHIFT, 556 CLK_SPI1_DIV_CON_15 = 15, 557 CLK_SPI1_DIV_CON_11 = 11, 558 CLK_SPI1_DIV_CON_7 = 7, 559 560 /* CLKSEL_CON32 */ 561 CLK_SPI2_PLL_SEL_SHIFT = 14, 562 CLK_SPI2_PLL_SEL_MASK = 0x3 << CLK_SPI2_PLL_SEL_SHIFT, 563 CLK_SPI2_PLL_SEL_DPLL = 0, 564 CLK_SPI2_DIV_CON_SHIFT = 0, 565 CLK_SPI2_DIV_CON_MASK = 0x7f << CLK_SPI2_DIV_CON_SHIFT, 566 CLK_SPI2_DIV_CON_15 = 15, 567 CLK_SPI2_DIV_CON_11 = 11, 568 CLK_SPI2_DIV_CON_7 = 7, 569 570 /* CLKSEL_CON36 */ 571 A_H_P_PERI_PLL_SEL_SHIFT = 6, 572 A_H_P_PERI_PLL_SEL_MASK = 0x3 << A_H_P_PERI_PLL_SEL_SHIFT, 573 A_H_P_PERI_PLL_SEL_DPLL = 0, 574 ACLK_PERI_DIV_CON_SHIFT = 0, 575 ACLK_PERI_DIV_CON_MASK = 0x1f << ACLK_PERI_DIV_CON_SHIFT, 576 ACLK_PERI_DIV_CON_7 = 7, 577 ACLK_PERI_DIV_CON_5 = 5, 578 ACLK_PERI_DIV_CON_3 = 3, 579 580 /* CLKSEL_CON37 */ 581 PCLK_PERI_DIV_CON_SHIFT = 8, 582 PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, 583 PCLK_PERI_DIV_CON_31 = 31, 584 PCLK_PERI_DIV_CON_27 = 27, 585 PCLK_PERI_DIV_CON_23 = 23, 586 PCLK_PERI_DIV_CON_15 = 15, 587 HCLK_PERI_DIV_CON_SHIFT = 0, 588 HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, 589 HCLK_PERI_DIV_CON_15 = 15, 590 HCLK_PERI_DIV_CON_13 = 13, 591 HCLK_PERI_DIV_CON_11 = 11, 592 HCLK_PERI_DIV_CON_7 = 7, 593 594 /* CLKSEL_CON38 */ 595 CLK_NANDC_SEL50_SHIFT = 15, 596 CLK_NANDC_SEL50_MASK = 0x1 << CLK_NANDC_SEL50_SHIFT, 597 CLK_NANDC_SEL50_EVEN = 0, 598 CLK_NANDC_SEL50_ALWAYS = 1, 599 CLK_NANDC_PLL_SEL_SHIFT = 6, 600 CLK_NANDC_PLL_SEL_MASK = 0x3 << CLK_NANDC_PLL_SEL_SHIFT, 601 CLK_NANDC_PLL_SEL_DPLL = 0, 602 CLK_NANDC_DIV_CON_SHIFT = 0, 603 CLK_NANDC_DIV_CON_MASK = 0x1f << CLK_NANDC_DIV_CON_SHIFT, 604 CLK_NANDC_DIV_CON_15 = 15, 605 CLK_NANDC_DIV_CON_13 = 13, 606 CLK_NANDC_DIV_CON_11 = 11, 607 CLK_NANDC_DIV_CON_7 = 7, 608 609 /* CLKSEL_CON39 */ 610 CLK_SDMMC_SEL50_SHIFT = 15, 611 CLK_SDMMC_SEL50_MASK = 0x1 << CLK_SDMMC_SEL50_SHIFT, 612 CLK_SDMMC_SEL50_EVEN = 0, 613 CLK_SDMMC_SEL50_ALWAYS = 1, 614 CLK_SDMMC_PLL_SEL_SHIFT = 8, 615 CLK_SDMMC_PLL_SEL_MASK = 0x3 << CLK_SDMMC_PLL_SEL_SHIFT, 616 CLK_SDMMC_PLL_SEL_DPLL = 0, 617 CLK_SDMMC_DIV_CON_SHIFT = 0, 618 CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT, 619 CLK_SDMMC_DIV_CON_31 = 31, 620 CLK_SDMMC_DIV_CON_27 = 27, 621 CLK_SDMMC_DIV_CON_23 = 23, 622 CLK_SDMMC_DIV_CON_15 = 15, 623 624 /* CLKSEL_CON40 */ 625 CLK_SDIO_SEL50_SHIFT = 15, 626 CLK_SDIO_SEL50_MASK = 0x1 << CLK_SDIO_SEL50_SHIFT, 627 CLK_SDIO_SEL50_EVEN = 0, 628 CLK_SDIO_SEL50_ALWAYS = 1, 629 CLK_SDIO_PLL_SEL_SHIFT = 8, 630 CLK_SDIO_PLL_SEL_MASK = 0x3 << CLK_SDIO_PLL_SEL_SHIFT, 631 CLK_SDIO_PLL_SEL_DPLL = 0, 632 CLK_SDIO_DIV_CON_SHIFT = 0, 633 CLK_SDIO_DIV_CON_MASK = 0xff << CLK_SDIO_DIV_CON_SHIFT, 634 CLK_SDIO_DIV_CON_4 = 4, 635 CLK_SDIO_DIV_CON_3 = 3, 636 CLK_SDIO_DIV_CON_2 = 2, 637 638 /* CLKSEL_CON41 */ 639 CLK_EMMC_SEL50_SHIFT = 15, 640 CLK_EMMC_SEL50_MASK = 0x1 << CLK_EMMC_SEL50_SHIFT, 641 CLK_EMMC_SEL50_EVEN = 0, 642 CLK_EMMC_SEL50_ALWAYS = 1, 643 CLK_EMMC_PLL_SEL_SHIFT = 8, 644 CLK_EMMC_PLL_SEL_MASK = 0x3 << CLK_EMMC_PLL_SEL_SHIFT, 645 CLK_EMMC_PLL_SEL_DPLL = 0, 646 CLK_EMMC_DIV_CON_SHIFT = 0, 647 CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT, 648 CLK_EMMC_DIV_CON_31 = 31, 649 CLK_EMMC_DIV_CON_27 = 27, 650 CLK_EMMC_DIV_CON_23 = 23, 651 CLK_EMMC_DIV_CON_15 = 15, 652 653 /* CLKSEL_CON42 */ 654 CLK_SFC_PLL_SEL_SHIFT = 14, 655 CLK_SFC_PLL_SEL_MASK = 0x3 << CLK_SFC_PLL_SEL_SHIFT, 656 CLK_SFC_PLL_SEL_DPLL = 0, 657 CLK_SFC_DIV_CON_SHIFT = 0, 658 CLK_SFC_DIV_CON_MASK = 0x7f << CLK_SFC_DIV_CON_SHIFT, 659 CLK_SFC_DIV_CON_65 = 65, 660 CLK_SFC_DIV_CON_53 = 53, 661 CLK_SFC_DIV_CON_49 = 49, 662 CLK_SFC_DIV_CON_31 = 31, 663 664 /* CLKSEL_CON43 */ 665 RMII_CLK_SEL_SHIFT = 15, 666 RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT, 667 RMII_CLK_SEL_100M = 1, 668 RMII_CLK_SEL_10M = 0, 669 RMII_EXTCLKSRC_SEL_SHIFT = 14, 670 RMII_EXTCLKSRC_SEL_MASK = 0x1 << RMII_EXTCLKSRC_SEL_SHIFT, 671 RMII_EXTCLKSRC_SEL_CLK_MAC = 0, 672 CLK_MAC_PLL_SEL_SHIFT = 6, 673 CLK_MAC_PLL_SEL_MASK = 0x3 << CLK_MAC_PLL_SEL_SHIFT, 674 CLK_MAC_PLL_SEL_DPLL = 0, 675 CLK_MAC_DIV_CON_SHIFT = 0, 676 CLK_MAC_DIV_CON_MASK = 0x1f << CLK_MAC_DIV_CON_SHIFT, 677 CLK_MAC_DIV_CON_31 = 31, 678 CLK_MAC_DIV_CON_23 = 23, 679 CLK_MAC_DIV_CON_25 = 25, 680 681 /* CLKSEL_CON44 */ 682 CLK_WIFI_SEL_SHIFT = 7, 683 CLK_WIFI_SEL_MASK = 0x1 << CLK_WIFI_SEL_SHIFT, 684 CLK_WIFI_SEL_CLK_WIFI = 1, 685 CLK_WIFI_PLL_SEL_SHIFT = 6, 686 CLK_WIFI_PLL_SEL_MASK = 0x1 << CLK_WIFI_PLL_SEL_SHIFT, 687 CLK_WIFI_PLL_SEL_DPLL = 0, 688 CLK_WIFI_DIV_CON_SHIFT = 0, 689 CLK_WIFI_DIV_CON_MASK = 0x3f << CLK_WIFI_DIV_CON_SHIFT, 690 CLK_WIFI_DIV_CON_39 = 39, 691 CLK_WIFI_DIV_CON_29 = 29, 692 CLK_WIFI_DIV_CON_49 = 49, 693 CLK_WIFI_DIV_CON_19 = 19, 694 695 /* CLKSEL_CON45 */ 696 PCLK_AUDIO_DIV_CON_SHIFT = 8, 697 PCLK_AUDIO_DIV_CON_MASK = 0x1f << PCLK_AUDIO_DIV_CON_SHIFT, 698 PCLK_AUDIO_DIV_CON_9 = 9, 699 H_PCLK_AUDIO_PLL_SEL_SHIFT = 6, 700 H_PCLK_AUDIO_PLL_SEL_MASK = 0x3 << H_PCLK_AUDIO_PLL_SEL_SHIFT, 701 H_PCLK_AUDIO_PLL_SEL_VPLL0 = 0, 702 HCLK_AUDIO_DIV_CON_SHIFT = 0, 703 HCLK_AUDIO_DIV_CON_MASK = 0x1f << HCLK_AUDIO_DIV_CON_SHIFT, 704 HCLK_AUDIO_DIV_CON_9 = 9, 705 706 /* CLKSEL_CON46 */ 707 CLK_PDM_SEL_SHIFT = 15, 708 CLK_PDM_SEL_MASK = 0x1 << CLK_PDM_SEL_SHIFT, 709 CLK_PDM_SEL_CLK_PDM = 0, 710 CLK_PDM_PLL_SEL_SHIFT = 8, 711 CLK_PDM_PLL_SEL_MASK = 0x3 << CLK_PDM_PLL_SEL_SHIFT, 712 CLK_PDM_PLL_SEL_VPLL0 = 0, 713 CLK_PDM_DIV_CON_SHIFT = 0, 714 CLK_PDM_DIV_CON_MASK = 0x7f << CLK_PDM_DIV_CON_SHIFT, 715 CLK_PDM_DIV_CON_15 = 15, 716 717 /* CLKSEL_CON48 */ 718 CLK_SPDIFTX_DIV_CON_SHIFT = 0, 719 CLK_SPDIFTX_DIV_CON_MASK = 0x7f << CLK_SPDIFTX_DIV_CON_SHIFT, 720 CLK_SPDIFTX_DIV_CON_15 = 15, 721 722 /* CLKSEL_CON52,CLKSEL_CON56,CLKSEL_CON60,CLKSEL_CON64 */ 723 I2S_8CH_OUT_SEL_SHIFT = 15, 724 I2S_8CH_OUT_SEL_MASK = 0x1 << I2S_8CH_OUT_SEL_SHIFT, 725 I2S_8CH_OUT_SEL_TX_RX = 0, 726 I2S_8CH_TX_RX_SEL_SHIFT = 12, 727 I2S_8CH_TX_RX_SEL_MASK = 0x1 << I2S_8CH_TX_RX_SEL_SHIFT, 728 I2S_8CH_TX_RX_SEL_TX = 0, 729 I2S_8CH_TX_SEL_SHIFT = 10, 730 I2S_8CH_TX_SEL_MASK = 0x3 << I2S_8CH_TX_SEL_SHIFT, 731 I2S_8CH_TX_SEL_TX = 0, 732 I2S_8CH_TX_PLL_SEL_SHIFT = 8, 733 I2S_8CH_TX_PLL_SEL_MASK = 0x3 << I2S_8CH_TX_PLL_SEL_SHIFT, 734 I2S_8CH_TX_PLL_SEL_VPLL1 = 1, 735 I2S_8CH_TX_DIV_CON_SHIFT = 0, 736 I2S_8CH_TX_DIV_CON_MASK = 0x7f << I2S_8CH_TX_DIV_CON_SHIFT, 737 I2S_8CH_TX_DIV_CON_17 = 17, 738 739 /* CLKSEL_CON54,CLKSEL_CON58,CLKSEL_CON62,CLKSEL_CON66 */ 740 I2S_8CH_RX_TX_SEL_SHIFT = 12, 741 I2S_8CH_RX_TX_SEL_MASK = 0x1 << I2S_8CH_RX_TX_SEL_SHIFT, 742 I2S_8CH_RX_TX_SEL_RX = 0, 743 I2S_8CH_RX_SEL_SHIFT = 10, 744 I2S_8CH_RX_SEL_MASK = 0x3 << I2S_8CH_RX_SEL_SHIFT, 745 I2S_8CH_RX_SEL_RX = 0, 746 I2S_8CH_RX_PLL_SEL_SHIFT = 8, 747 I2S_8CH_RX_PLL_SEL_MASK = 0x3 << I2S_8CH_RX_PLL_SEL_SHIFT, 748 I2S_8CH_RX_PLL_SEL_VPLL0 = 0, 749 I2S_8CH_RX_DIV_CON_SHIFT = 0, 750 I2S_8CH_RX_DIV_CON_MASK = 0x7f << I2S_8CH_RX_DIV_CON_SHIFT, 751 I2S_8CH_RX_DIV_CON_19 = 19, 752 753 /* SOFTRST_CON1 */ 754 PRESETN_DDRPHY_REQ_SHIFT = 14, 755 PRESETN_DDRPHY_REQ_MASK = 0x1 << PRESETN_DDRPHY_REQ_SHIFT, 756 PRESETN_DDRPHY_REQ_EN = 1, 757 PRESETN_DDRPHY_REQ_DIS = 0, 758 759 RESETN_DDRPHYDIV_REQ_SHIFT = 13, 760 RESETN_DDRPHYDIV_REQ_MASK = 0x1 << RESETN_DDRPHYDIV_REQ_SHIFT, 761 RESETN_DDRPHYDIV_REQ_EN = 1, 762 RESETN_DDRPHYDIV_REQ_DIS = 0, 763 764 RESETN_DDRPHY_REQ_SHIFT = 12, 765 RESETN_DDRPHY_REQ_MASK = 0x1 << RESETN_DDRPHY_REQ_SHIFT, 766 RESETN_DDRPHY_REQ_EN = 1, 767 RESETN_DDRPHY_REQ_DIS = 0, 768 769 PRESETN_DDRUPCTL_REQ_SHIFT = 6, 770 PRESETN_DDRUPCTL_REQ_MASK = 0x1 << PRESETN_DDRUPCTL_REQ_SHIFT, 771 PRESETN_DDRUPCTL_REQ_EN = 1, 772 PRESETN_DDRUPCTL_REQ_DIS = 0, 773 774 RESETN_DDRUPCTL_REQ_SHIFT = 4, 775 RESETN_DDRUPCTL_REQ_MASK = 0x1 << RESETN_DDRUPCTL_REQ_SHIFT, 776 RESETN_DDRUPCTL_REQ_EN = 1, 777 RESETN_DDRUPCTL_REQ_DIS = 0, 778 779 /* CLKGATE_CON4 */ 780 CLK_PMU_PVTM_CLK_EN_SHIFT = 4, 781 CLK_PMU_PVTM_CLK_EN_MASK = 0x1 << CLK_PMU_PVTM_CLK_EN_SHIFT, 782 CLK_PMU_PVTM_CLK_EN = 0, 783 784 /* SOFTRST_CON5 */ 785 RESETN_PMU_PVTM_REQ_SHIFT = 1, 786 RESETN_PMU_PVTM_REQ_MASK = 0x1 << RESETN_PMU_PVTM_REQ_SHIFT, 787 RESETN_PMU_PVTM_REQ_ACT = 1, 788 RESETN_PMU_PVTM_REQ_DIS = 0, 789 }; 790 791 #endif 792