clk/rockchip/clk_rk3308.c

78 	[DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
186 		priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],  in rk3308_clk_get_pll_rate()
187 						      priv->cru, DPLL);  in rk3308_clk_get_pll_rate()
275 		pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],  in rk3308_mac_set_clk()
276 						 priv->cru, DPLL);  in rk3308_mac_set_clk()
943 		rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],  in rk3308_clk_get_rate()
944 					     priv->cru, DPLL);  in rk3308_clk_get_rate()
1024 		ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru,  in rk3308_clk_set_rate()
1025 					    DPLL, rate);  in rk3308_clk_set_rate()
1026 		priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],  in rk3308_clk_set_rate()
1027 						      priv->cru, DPLL);  in rk3308_clk_set_rate()