1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2006 Dave Airlie <airlied@linux.ie>
3*4882a593Smuzhiyun * Copyright © 2006-2007 Intel Corporation
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next
13*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the
14*4882a593Smuzhiyun * Software.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * Authors:
25*4882a593Smuzhiyun * Eric Anholt <eric@anholt.net>
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <linux/i2c.h>
29*4882a593Smuzhiyun #include <linux/slab.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
32*4882a593Smuzhiyun #include <drm/drm_crtc.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include "i915_drv.h"
35*4882a593Smuzhiyun #include "intel_connector.h"
36*4882a593Smuzhiyun #include "intel_display_types.h"
37*4882a593Smuzhiyun #include "intel_dvo.h"
38*4882a593Smuzhiyun #include "intel_dvo_dev.h"
39*4882a593Smuzhiyun #include "intel_gmbus.h"
40*4882a593Smuzhiyun #include "intel_panel.h"
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define INTEL_DVO_CHIP_NONE 0
43*4882a593Smuzhiyun #define INTEL_DVO_CHIP_LVDS 1
44*4882a593Smuzhiyun #define INTEL_DVO_CHIP_TMDS 2
45*4882a593Smuzhiyun #define INTEL_DVO_CHIP_TVOUT 4
46*4882a593Smuzhiyun #define INTEL_DVO_CHIP_LVDS_NO_FIXED 5
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define SIL164_ADDR 0x38
49*4882a593Smuzhiyun #define CH7xxx_ADDR 0x76
50*4882a593Smuzhiyun #define TFP410_ADDR 0x38
51*4882a593Smuzhiyun #define NS2501_ADDR 0x38
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static const struct intel_dvo_device intel_dvo_devices[] = {
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun .type = INTEL_DVO_CHIP_TMDS,
56*4882a593Smuzhiyun .name = "sil164",
57*4882a593Smuzhiyun .dvo_reg = DVOC,
58*4882a593Smuzhiyun .dvo_srcdim_reg = DVOC_SRCDIM,
59*4882a593Smuzhiyun .slave_addr = SIL164_ADDR,
60*4882a593Smuzhiyun .dev_ops = &sil164_ops,
61*4882a593Smuzhiyun },
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun .type = INTEL_DVO_CHIP_TMDS,
64*4882a593Smuzhiyun .name = "ch7xxx",
65*4882a593Smuzhiyun .dvo_reg = DVOC,
66*4882a593Smuzhiyun .dvo_srcdim_reg = DVOC_SRCDIM,
67*4882a593Smuzhiyun .slave_addr = CH7xxx_ADDR,
68*4882a593Smuzhiyun .dev_ops = &ch7xxx_ops,
69*4882a593Smuzhiyun },
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun .type = INTEL_DVO_CHIP_TMDS,
72*4882a593Smuzhiyun .name = "ch7xxx",
73*4882a593Smuzhiyun .dvo_reg = DVOC,
74*4882a593Smuzhiyun .dvo_srcdim_reg = DVOC_SRCDIM,
75*4882a593Smuzhiyun .slave_addr = 0x75, /* For some ch7010 */
76*4882a593Smuzhiyun .dev_ops = &ch7xxx_ops,
77*4882a593Smuzhiyun },
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun .type = INTEL_DVO_CHIP_LVDS,
80*4882a593Smuzhiyun .name = "ivch",
81*4882a593Smuzhiyun .dvo_reg = DVOA,
82*4882a593Smuzhiyun .dvo_srcdim_reg = DVOA_SRCDIM,
83*4882a593Smuzhiyun .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
84*4882a593Smuzhiyun .dev_ops = &ivch_ops,
85*4882a593Smuzhiyun },
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun .type = INTEL_DVO_CHIP_TMDS,
88*4882a593Smuzhiyun .name = "tfp410",
89*4882a593Smuzhiyun .dvo_reg = DVOC,
90*4882a593Smuzhiyun .dvo_srcdim_reg = DVOC_SRCDIM,
91*4882a593Smuzhiyun .slave_addr = TFP410_ADDR,
92*4882a593Smuzhiyun .dev_ops = &tfp410_ops,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun .type = INTEL_DVO_CHIP_LVDS,
96*4882a593Smuzhiyun .name = "ch7017",
97*4882a593Smuzhiyun .dvo_reg = DVOC,
98*4882a593Smuzhiyun .dvo_srcdim_reg = DVOC_SRCDIM,
99*4882a593Smuzhiyun .slave_addr = 0x75,
100*4882a593Smuzhiyun .gpio = GMBUS_PIN_DPB,
101*4882a593Smuzhiyun .dev_ops = &ch7017_ops,
102*4882a593Smuzhiyun },
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun .type = INTEL_DVO_CHIP_LVDS_NO_FIXED,
105*4882a593Smuzhiyun .name = "ns2501",
106*4882a593Smuzhiyun .dvo_reg = DVOB,
107*4882a593Smuzhiyun .dvo_srcdim_reg = DVOB_SRCDIM,
108*4882a593Smuzhiyun .slave_addr = NS2501_ADDR,
109*4882a593Smuzhiyun .dev_ops = &ns2501_ops,
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun struct intel_dvo {
114*4882a593Smuzhiyun struct intel_encoder base;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun struct intel_dvo_device dev;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun struct intel_connector *attached_connector;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun bool panel_wants_dither;
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
enc_to_dvo(struct intel_encoder * encoder)123*4882a593Smuzhiyun static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun return container_of(encoder, struct intel_dvo, base);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
intel_attached_dvo(struct intel_connector * connector)128*4882a593Smuzhiyun static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun return enc_to_dvo(intel_attached_encoder(connector));
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
intel_dvo_connector_get_hw_state(struct intel_connector * connector)133*4882a593Smuzhiyun static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct drm_device *dev = connector->base.dev;
136*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(dev);
137*4882a593Smuzhiyun struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
138*4882a593Smuzhiyun u32 tmp;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (!(tmp & DVO_ENABLE))
143*4882a593Smuzhiyun return false;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
intel_dvo_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)148*4882a593Smuzhiyun static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
149*4882a593Smuzhiyun enum pipe *pipe)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
152*4882a593Smuzhiyun struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
153*4882a593Smuzhiyun u32 tmp;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return tmp & DVO_ENABLE;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
intel_dvo_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)162*4882a593Smuzhiyun static void intel_dvo_get_config(struct intel_encoder *encoder,
163*4882a593Smuzhiyun struct intel_crtc_state *pipe_config)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
166*4882a593Smuzhiyun struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
167*4882a593Smuzhiyun u32 tmp, flags = 0;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg);
172*4882a593Smuzhiyun if (tmp & DVO_HSYNC_ACTIVE_HIGH)
173*4882a593Smuzhiyun flags |= DRM_MODE_FLAG_PHSYNC;
174*4882a593Smuzhiyun else
175*4882a593Smuzhiyun flags |= DRM_MODE_FLAG_NHSYNC;
176*4882a593Smuzhiyun if (tmp & DVO_VSYNC_ACTIVE_HIGH)
177*4882a593Smuzhiyun flags |= DRM_MODE_FLAG_PVSYNC;
178*4882a593Smuzhiyun else
179*4882a593Smuzhiyun flags |= DRM_MODE_FLAG_NVSYNC;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun pipe_config->hw.adjusted_mode.flags |= flags;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
intel_disable_dvo(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)186*4882a593Smuzhiyun static void intel_disable_dvo(struct intel_atomic_state *state,
187*4882a593Smuzhiyun struct intel_encoder *encoder,
188*4882a593Smuzhiyun const struct intel_crtc_state *old_crtc_state,
189*4882a593Smuzhiyun const struct drm_connector_state *old_conn_state)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
192*4882a593Smuzhiyun struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
193*4882a593Smuzhiyun i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
194*4882a593Smuzhiyun u32 temp = intel_de_read(dev_priv, dvo_reg);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
197*4882a593Smuzhiyun intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE);
198*4882a593Smuzhiyun intel_de_read(dev_priv, dvo_reg);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
intel_enable_dvo(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)201*4882a593Smuzhiyun static void intel_enable_dvo(struct intel_atomic_state *state,
202*4882a593Smuzhiyun struct intel_encoder *encoder,
203*4882a593Smuzhiyun const struct intel_crtc_state *pipe_config,
204*4882a593Smuzhiyun const struct drm_connector_state *conn_state)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
207*4882a593Smuzhiyun struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
208*4882a593Smuzhiyun i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
209*4882a593Smuzhiyun u32 temp = intel_de_read(dev_priv, dvo_reg);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
212*4882a593Smuzhiyun &pipe_config->hw.mode,
213*4882a593Smuzhiyun &pipe_config->hw.adjusted_mode);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE);
216*4882a593Smuzhiyun intel_de_read(dev_priv, dvo_reg);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun static enum drm_mode_status
intel_dvo_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)222*4882a593Smuzhiyun intel_dvo_mode_valid(struct drm_connector *connector,
223*4882a593Smuzhiyun struct drm_display_mode *mode)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector));
226*4882a593Smuzhiyun const struct drm_display_mode *fixed_mode =
227*4882a593Smuzhiyun to_intel_connector(connector)->panel.fixed_mode;
228*4882a593Smuzhiyun int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
229*4882a593Smuzhiyun int target_clock = mode->clock;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
232*4882a593Smuzhiyun return MODE_NO_DBLESCAN;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* XXX: Validate clock range */
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun if (fixed_mode) {
237*4882a593Smuzhiyun if (mode->hdisplay > fixed_mode->hdisplay)
238*4882a593Smuzhiyun return MODE_PANEL;
239*4882a593Smuzhiyun if (mode->vdisplay > fixed_mode->vdisplay)
240*4882a593Smuzhiyun return MODE_PANEL;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun target_clock = fixed_mode->clock;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (target_clock > max_dotclk)
246*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
intel_dvo_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)251*4882a593Smuzhiyun static int intel_dvo_compute_config(struct intel_encoder *encoder,
252*4882a593Smuzhiyun struct intel_crtc_state *pipe_config,
253*4882a593Smuzhiyun struct drm_connector_state *conn_state)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
256*4882a593Smuzhiyun const struct drm_display_mode *fixed_mode =
257*4882a593Smuzhiyun intel_dvo->attached_connector->panel.fixed_mode;
258*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun /*
261*4882a593Smuzhiyun * If we have timings from the BIOS for the panel, put them in
262*4882a593Smuzhiyun * to the adjusted mode. The CRTC will be set up for this mode,
263*4882a593Smuzhiyun * with the panel scaling set up to source from the H/VDisplay
264*4882a593Smuzhiyun * of the original mode.
265*4882a593Smuzhiyun */
266*4882a593Smuzhiyun if (fixed_mode)
267*4882a593Smuzhiyun intel_fixed_panel_mode(fixed_mode, adjusted_mode);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
270*4882a593Smuzhiyun return -EINVAL;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun return 0;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
intel_dvo_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)277*4882a593Smuzhiyun static void intel_dvo_pre_enable(struct intel_atomic_state *state,
278*4882a593Smuzhiyun struct intel_encoder *encoder,
279*4882a593Smuzhiyun const struct intel_crtc_state *pipe_config,
280*4882a593Smuzhiyun const struct drm_connector_state *conn_state)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
283*4882a593Smuzhiyun struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
284*4882a593Smuzhiyun const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
285*4882a593Smuzhiyun struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
286*4882a593Smuzhiyun enum pipe pipe = crtc->pipe;
287*4882a593Smuzhiyun u32 dvo_val;
288*4882a593Smuzhiyun i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
289*4882a593Smuzhiyun i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /* Save the data order, since I don't know what it should be set to. */
292*4882a593Smuzhiyun dvo_val = intel_de_read(dev_priv, dvo_reg) &
293*4882a593Smuzhiyun (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
294*4882a593Smuzhiyun dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
295*4882a593Smuzhiyun DVO_BLANK_ACTIVE_HIGH;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun dvo_val |= DVO_PIPE_SEL(pipe);
298*4882a593Smuzhiyun dvo_val |= DVO_PIPE_STALL;
299*4882a593Smuzhiyun if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
300*4882a593Smuzhiyun dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
301*4882a593Smuzhiyun if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
302*4882a593Smuzhiyun dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /*I915_WRITE(DVOB_SRCDIM,
305*4882a593Smuzhiyun (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
306*4882a593Smuzhiyun (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
307*4882a593Smuzhiyun intel_de_write(dev_priv, dvo_srcdim_reg,
308*4882a593Smuzhiyun (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
309*4882a593Smuzhiyun /*I915_WRITE(DVOB, dvo_val);*/
310*4882a593Smuzhiyun intel_de_write(dev_priv, dvo_reg, dvo_val);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun static enum drm_connector_status
intel_dvo_detect(struct drm_connector * connector,bool force)314*4882a593Smuzhiyun intel_dvo_detect(struct drm_connector *connector, bool force)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun struct drm_i915_private *i915 = to_i915(connector->dev);
317*4882a593Smuzhiyun struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector));
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
320*4882a593Smuzhiyun connector->base.id, connector->name);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun if (!INTEL_DISPLAY_ENABLED(i915))
323*4882a593Smuzhiyun return connector_status_disconnected;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
intel_dvo_get_modes(struct drm_connector * connector)328*4882a593Smuzhiyun static int intel_dvo_get_modes(struct drm_connector *connector)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun struct drm_i915_private *dev_priv = to_i915(connector->dev);
331*4882a593Smuzhiyun const struct drm_display_mode *fixed_mode =
332*4882a593Smuzhiyun to_intel_connector(connector)->panel.fixed_mode;
333*4882a593Smuzhiyun int num_modes;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun /*
336*4882a593Smuzhiyun * We should probably have an i2c driver get_modes function for those
337*4882a593Smuzhiyun * devices which will have a fixed set of modes determined by the chip
338*4882a593Smuzhiyun * (TV-out, for example), but for now with just TMDS and LVDS,
339*4882a593Smuzhiyun * that's not the case.
340*4882a593Smuzhiyun */
341*4882a593Smuzhiyun num_modes = intel_ddc_get_modes(connector,
342*4882a593Smuzhiyun intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
343*4882a593Smuzhiyun if (num_modes)
344*4882a593Smuzhiyun return num_modes;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun if (fixed_mode) {
347*4882a593Smuzhiyun struct drm_display_mode *mode;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun mode = drm_mode_duplicate(connector->dev, fixed_mode);
350*4882a593Smuzhiyun if (mode) {
351*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
352*4882a593Smuzhiyun num_modes++;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun return num_modes;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun static const struct drm_connector_funcs intel_dvo_connector_funcs = {
360*4882a593Smuzhiyun .detect = intel_dvo_detect,
361*4882a593Smuzhiyun .late_register = intel_connector_register,
362*4882a593Smuzhiyun .early_unregister = intel_connector_unregister,
363*4882a593Smuzhiyun .destroy = intel_connector_destroy,
364*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
365*4882a593Smuzhiyun .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
366*4882a593Smuzhiyun .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
367*4882a593Smuzhiyun };
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
370*4882a593Smuzhiyun .mode_valid = intel_dvo_mode_valid,
371*4882a593Smuzhiyun .get_modes = intel_dvo_get_modes,
372*4882a593Smuzhiyun };
373*4882a593Smuzhiyun
intel_dvo_enc_destroy(struct drm_encoder * encoder)374*4882a593Smuzhiyun static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (intel_dvo->dev.dev_ops->destroy)
379*4882a593Smuzhiyun intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun intel_encoder_destroy(encoder);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
385*4882a593Smuzhiyun .destroy = intel_dvo_enc_destroy,
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun /*
389*4882a593Smuzhiyun * Attempts to get a fixed panel timing for LVDS (currently only the i830).
390*4882a593Smuzhiyun *
391*4882a593Smuzhiyun * Other chips with DVO LVDS will need to extend this to deal with the LVDS
392*4882a593Smuzhiyun * chip being on DVOB/C and having multiple pipes.
393*4882a593Smuzhiyun */
394*4882a593Smuzhiyun static struct drm_display_mode *
intel_dvo_get_current_mode(struct intel_encoder * encoder)395*4882a593Smuzhiyun intel_dvo_get_current_mode(struct intel_encoder *encoder)
396*4882a593Smuzhiyun {
397*4882a593Smuzhiyun struct drm_display_mode *mode;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun mode = intel_encoder_current_mode(encoder);
400*4882a593Smuzhiyun if (mode) {
401*4882a593Smuzhiyun DRM_DEBUG_KMS("using current (BIOS) mode: ");
402*4882a593Smuzhiyun drm_mode_debug_printmodeline(mode);
403*4882a593Smuzhiyun mode->type |= DRM_MODE_TYPE_PREFERRED;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun return mode;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
intel_dvo_port(i915_reg_t dvo_reg)409*4882a593Smuzhiyun static enum port intel_dvo_port(i915_reg_t dvo_reg)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun if (i915_mmio_reg_equal(dvo_reg, DVOA))
412*4882a593Smuzhiyun return PORT_A;
413*4882a593Smuzhiyun else if (i915_mmio_reg_equal(dvo_reg, DVOB))
414*4882a593Smuzhiyun return PORT_B;
415*4882a593Smuzhiyun else
416*4882a593Smuzhiyun return PORT_C;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
intel_dvo_init(struct drm_i915_private * dev_priv)419*4882a593Smuzhiyun void intel_dvo_init(struct drm_i915_private *dev_priv)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun struct intel_encoder *intel_encoder;
422*4882a593Smuzhiyun struct intel_dvo *intel_dvo;
423*4882a593Smuzhiyun struct intel_connector *intel_connector;
424*4882a593Smuzhiyun int i;
425*4882a593Smuzhiyun int encoder_type = DRM_MODE_ENCODER_NONE;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
428*4882a593Smuzhiyun if (!intel_dvo)
429*4882a593Smuzhiyun return;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun intel_connector = intel_connector_alloc();
432*4882a593Smuzhiyun if (!intel_connector) {
433*4882a593Smuzhiyun kfree(intel_dvo);
434*4882a593Smuzhiyun return;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun intel_dvo->attached_connector = intel_connector;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun intel_encoder = &intel_dvo->base;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun intel_encoder->disable = intel_disable_dvo;
442*4882a593Smuzhiyun intel_encoder->enable = intel_enable_dvo;
443*4882a593Smuzhiyun intel_encoder->get_hw_state = intel_dvo_get_hw_state;
444*4882a593Smuzhiyun intel_encoder->get_config = intel_dvo_get_config;
445*4882a593Smuzhiyun intel_encoder->compute_config = intel_dvo_compute_config;
446*4882a593Smuzhiyun intel_encoder->pre_enable = intel_dvo_pre_enable;
447*4882a593Smuzhiyun intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun /* Now, try to find a controller */
450*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
451*4882a593Smuzhiyun struct drm_connector *connector = &intel_connector->base;
452*4882a593Smuzhiyun const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
453*4882a593Smuzhiyun struct i2c_adapter *i2c;
454*4882a593Smuzhiyun int gpio;
455*4882a593Smuzhiyun bool dvoinit;
456*4882a593Smuzhiyun enum pipe pipe;
457*4882a593Smuzhiyun u32 dpll[I915_MAX_PIPES];
458*4882a593Smuzhiyun enum port port;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun /*
461*4882a593Smuzhiyun * Allow the I2C driver info to specify the GPIO to be used in
462*4882a593Smuzhiyun * special cases, but otherwise default to what's defined
463*4882a593Smuzhiyun * in the spec.
464*4882a593Smuzhiyun */
465*4882a593Smuzhiyun if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
466*4882a593Smuzhiyun gpio = dvo->gpio;
467*4882a593Smuzhiyun else if (dvo->type == INTEL_DVO_CHIP_LVDS)
468*4882a593Smuzhiyun gpio = GMBUS_PIN_SSC;
469*4882a593Smuzhiyun else
470*4882a593Smuzhiyun gpio = GMBUS_PIN_DPB;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun /*
473*4882a593Smuzhiyun * Set up the I2C bus necessary for the chip we're probing.
474*4882a593Smuzhiyun * It appears that everything is on GPIOE except for panels
475*4882a593Smuzhiyun * on i830 laptops, which are on GPIOB (DVOA).
476*4882a593Smuzhiyun */
477*4882a593Smuzhiyun i2c = intel_gmbus_get_adapter(dev_priv, gpio);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun intel_dvo->dev = *dvo;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun /*
482*4882a593Smuzhiyun * GMBUS NAK handling seems to be unstable, hence let the
483*4882a593Smuzhiyun * transmitter detection run in bit banging mode for now.
484*4882a593Smuzhiyun */
485*4882a593Smuzhiyun intel_gmbus_force_bit(i2c, true);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun /*
488*4882a593Smuzhiyun * ns2501 requires the DVO 2x clock before it will
489*4882a593Smuzhiyun * respond to i2c accesses, so make sure we have
490*4882a593Smuzhiyun * have the clock enabled before we attempt to
491*4882a593Smuzhiyun * initialize the device.
492*4882a593Smuzhiyun */
493*4882a593Smuzhiyun for_each_pipe(dev_priv, pipe) {
494*4882a593Smuzhiyun dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe));
495*4882a593Smuzhiyun intel_de_write(dev_priv, DPLL(pipe),
496*4882a593Smuzhiyun dpll[pipe] | DPLL_DVO_2X_MODE);
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun /* restore the DVO 2x clock state to original */
502*4882a593Smuzhiyun for_each_pipe(dev_priv, pipe) {
503*4882a593Smuzhiyun intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun intel_gmbus_force_bit(i2c, false);
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun if (!dvoinit)
509*4882a593Smuzhiyun continue;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun port = intel_dvo_port(dvo->dvo_reg);
512*4882a593Smuzhiyun drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
513*4882a593Smuzhiyun &intel_dvo_enc_funcs, encoder_type,
514*4882a593Smuzhiyun "DVO %c", port_name(port));
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun intel_encoder->type = INTEL_OUTPUT_DVO;
517*4882a593Smuzhiyun intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
518*4882a593Smuzhiyun intel_encoder->port = port;
519*4882a593Smuzhiyun intel_encoder->pipe_mask = ~0;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun if (dvo->type != INTEL_DVO_CHIP_LVDS)
522*4882a593Smuzhiyun intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
523*4882a593Smuzhiyun (1 << INTEL_OUTPUT_DVO);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun switch (dvo->type) {
526*4882a593Smuzhiyun case INTEL_DVO_CHIP_TMDS:
527*4882a593Smuzhiyun intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT |
528*4882a593Smuzhiyun DRM_CONNECTOR_POLL_DISCONNECT;
529*4882a593Smuzhiyun drm_connector_init(&dev_priv->drm, connector,
530*4882a593Smuzhiyun &intel_dvo_connector_funcs,
531*4882a593Smuzhiyun DRM_MODE_CONNECTOR_DVII);
532*4882a593Smuzhiyun encoder_type = DRM_MODE_ENCODER_TMDS;
533*4882a593Smuzhiyun break;
534*4882a593Smuzhiyun case INTEL_DVO_CHIP_LVDS_NO_FIXED:
535*4882a593Smuzhiyun case INTEL_DVO_CHIP_LVDS:
536*4882a593Smuzhiyun drm_connector_init(&dev_priv->drm, connector,
537*4882a593Smuzhiyun &intel_dvo_connector_funcs,
538*4882a593Smuzhiyun DRM_MODE_CONNECTOR_LVDS);
539*4882a593Smuzhiyun encoder_type = DRM_MODE_ENCODER_LVDS;
540*4882a593Smuzhiyun break;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun drm_connector_helper_add(connector,
544*4882a593Smuzhiyun &intel_dvo_connector_helper_funcs);
545*4882a593Smuzhiyun connector->display_info.subpixel_order = SubPixelHorizontalRGB;
546*4882a593Smuzhiyun connector->interlace_allowed = false;
547*4882a593Smuzhiyun connector->doublescan_allowed = false;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun intel_connector_attach_encoder(intel_connector, intel_encoder);
550*4882a593Smuzhiyun if (dvo->type == INTEL_DVO_CHIP_LVDS) {
551*4882a593Smuzhiyun /*
552*4882a593Smuzhiyun * For our LVDS chipsets, we should hopefully be able
553*4882a593Smuzhiyun * to dig the fixed panel mode out of the BIOS data.
554*4882a593Smuzhiyun * However, it's in a different format from the BIOS
555*4882a593Smuzhiyun * data on chipsets with integrated LVDS (stored in AIM
556*4882a593Smuzhiyun * headers, likely), so for now, just get the current
557*4882a593Smuzhiyun * mode being output through DVO.
558*4882a593Smuzhiyun */
559*4882a593Smuzhiyun intel_panel_init(&intel_connector->panel,
560*4882a593Smuzhiyun intel_dvo_get_current_mode(intel_encoder),
561*4882a593Smuzhiyun NULL);
562*4882a593Smuzhiyun intel_dvo->panel_wants_dither = true;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun return;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun kfree(intel_dvo);
569*4882a593Smuzhiyun kfree(intel_connector);
570*4882a593Smuzhiyun }
571