1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3568_H 8 #define _ASM_ARCH_CRU_RK3568_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (816 * MHz) 15 #define GPLL_HZ (1188 * MHz) 16 #define CPLL_HZ (1000 * MHz) 17 #define PPLL_HZ (200 * MHz) 18 19 /* RK3568 pll id */ 20 enum rk3568_pll_id { 21 APLL, 22 DPLL, 23 CPLL, 24 GPLL, 25 NPLL, 26 VPLL, 27 PPLL, 28 HPLL, 29 PLL_COUNT, 30 }; 31 32 struct rk3568_clk_info { 33 unsigned long id; 34 char *name; 35 bool is_cru; 36 }; 37 38 /* Private data for the clock driver - used by rockchip_get_cru() */ 39 struct rk3568_pmuclk_priv { 40 struct rk3568_pmucru *pmucru; 41 ulong ppll_hz; 42 ulong hpll_hz; 43 }; 44 45 struct rk3568_clk_priv { 46 struct rk3568_cru *cru; 47 struct rk3568_grf *grf; 48 ulong ppll_hz; 49 ulong hpll_hz; 50 ulong gpll_hz; 51 ulong cpll_hz; 52 ulong npll_hz; 53 ulong vpll_hz; 54 ulong armclk_hz; 55 ulong armclk_enter_hz; 56 ulong armclk_init_hz; 57 bool sync_kernel; 58 bool set_armclk_rate; 59 }; 60 61 struct rk3568_pll { 62 unsigned int con0; 63 unsigned int con1; 64 unsigned int con2; 65 unsigned int con3; 66 unsigned int con4; 67 unsigned int reserved0[3]; 68 }; 69 70 struct rk3568_pmucru { 71 struct rk3568_pll pll[2];/* Address Offset: 0x0000 */ 72 unsigned int reserved0[16];/* Address Offset: 0x0040 */ 73 unsigned int mode_con00;/* Address Offset: 0x0080 */ 74 unsigned int reserved1[31];/* Address Offset: 0x0084 */ 75 unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */ 76 unsigned int reserved2[22];/* Address Offset: 0x0128 */ 77 unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */ 78 unsigned int reserved3[29];/* Address Offset: 0x018C */ 79 unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */ 80 }; 81 82 check_member(rk3568_pmucru, mode_con00, 0x80); 83 check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200); 84 85 struct rk3568_cru { 86 struct rk3568_pll pll[6]; 87 unsigned int mode_con00;/* Address Offset: 0x00C0 */ 88 unsigned int misc_con[3];/* Address Offset: 0x00C4 */ 89 unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */ 90 unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */ 91 unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */ 92 unsigned int glb_rst_con;/* Address Offset: 0x00DC */ 93 unsigned int glb_rst_st;/* Address Offset: 0x00E0 */ 94 unsigned int reserved0[7];/* Address Offset: 0x00E4 */ 95 unsigned int clksel_con[85]; /* Address Offset: 0x0100 */ 96 unsigned int reserved1[43];/* Address Offset: 0x0254 */ 97 unsigned int clkgate_con[36];/* Address Offset: 0x0300 */ 98 unsigned int reserved2[28]; /* Address Offset: 0x0390 */ 99 unsigned int softrst_con[30];/* Address Offset: 0x0400 */ 100 unsigned int reserved3[2];/* Address Offset: 0x0478 */ 101 unsigned int ssgtbl[32];/* Address Offset: 0x0480 */ 102 unsigned int reserved4[32];/* Address Offset: 0x0500 */ 103 unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */ 104 unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */ 105 unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */ 106 unsigned int emmc_con[2];/* Address Offset: 0x0598 */ 107 }; 108 109 check_member(rk3568_cru, mode_con00, 0xc0); 110 check_member(rk3568_cru, softrst_con[0], 0x400); 111 112 struct pll_rate_table { 113 unsigned long rate; 114 unsigned int fbdiv; 115 unsigned int postdiv1; 116 unsigned int refdiv; 117 unsigned int postdiv2; 118 unsigned int dsmpd; 119 unsigned int frac; 120 }; 121 122 #define RK3568_PMU_MODE 0x80 123 #define RK3568_PMU_PLL_CON(x) ((x) * 0x4) 124 #define RK3568_PLL_CON(x) ((x) * 0x4) 125 #define RK3568_MODE_CON 0xc0 126 127 enum { 128 /* CRU_PMU_CLK_SEL0_CON */ 129 RTC32K_SEL_SHIFT = 6, 130 RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, 131 RTC32K_SEL_PMUPVTM = 0, 132 RTC32K_SEL_OSC1_32K, 133 RTC32K_SEL_OSC0_DIV32K, 134 135 /* CRU_PMU_CLK_SEL1_CON */ 136 RTC32K_FRAC_NUMERATOR_SHIFT = 16, 137 RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 138 RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 139 RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 140 141 /* CRU_PMU_CLK_SEL2_CON */ 142 PCLK_PDPMU_SEL_SHIFT = 15, 143 PCLK_PDPMU_SEL_MASK = 1 << PCLK_PDPMU_SEL_SHIFT, 144 PCLK_PDPMU_SEL_PPLL = 0, 145 PCLK_PDPMU_SEL_GPLL, 146 PCLK_PDPMU_DIV_SHIFT = 0, 147 PCLK_PDPMU_DIV_MASK = 0x1f, 148 149 /* CRU_PMU_CLK_SEL3_CON */ 150 CLK_I2C0_DIV_SHIFT = 0, 151 CLK_I2C0_DIV_MASK = 0x7f, 152 153 /* CRU_PMU_CLK_SEL6_CON */ 154 CLK_PWM0_SEL_SHIFT = 7, 155 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 156 CLK_PWM0_SEL_XIN24M = 0, 157 CLK_PWM0_SEL_PPLL, 158 CLK_PWM0_DIV_SHIFT = 0, 159 CLK_PWM0_DIV_MASK = 0x7f, 160 161 /* CRU_CLK_SEL0_CON */ 162 CLK_CORE_PRE_SEL_SHIFT = 7, 163 CLK_CORE_PRE_SEL_MASK = 1 << CLK_CORE_PRE_SEL_SHIFT, 164 CLK_CORE_PRE_SEL_SRC = 0, 165 CLK_CORE_PRE_SEL_APLL, 166 167 /* CRU_CLK_SEL2_CON */ 168 SCLK_CORE_PRE_SEL_SHIFT = 15, 169 SCLK_CORE_PRE_SEL_MASK = 1 << SCLK_CORE_PRE_SEL_SHIFT, 170 SCLK_CORE_PRE_SEL_SRC = 0, 171 SCLK_CORE_PRE_SEL_NPLL, 172 SCLK_CORE_SRC_SEL_SHIFT = 8, 173 SCLK_CORE_SRC_SEL_MASK = 3 << SCLK_CORE_SRC_SEL_SHIFT, 174 SCLK_CORE_SRC_SEL_APLL = 0, 175 SCLK_CORE_SRC_SEL_GPLL, 176 SCLK_CORE_SRC_SEL_NPLL, 177 SCLK_CORE_SRC_DIV_SHIFT = 0, 178 SCLK_CORE_SRC_DIV_MASK = 0x1f << SCLK_CORE_SRC_DIV_SHIFT, 179 180 /* CRU_CLK_SEL3_CON */ 181 GICCLK_CORE_DIV_SHIFT = 8, 182 GICCLK_CORE_DIV_MASK = 0x1f << GICCLK_CORE_DIV_SHIFT, 183 ATCLK_CORE_DIV_SHIFT = 0, 184 ATCLK_CORE_DIV_MASK = 0x1f << ATCLK_CORE_DIV_SHIFT, 185 186 /* CRU_CLK_SEL4_CON */ 187 PERIPHCLK_CORE_PRE_DIV_SHIFT = 8, 188 PERIPHCLK_CORE_PRE_DIV_MASK = 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT, 189 PCLK_CORE_PRE_DIV_SHIFT = 0, 190 PCLK_CORE_PRE_DIV_MASK = 0x1f << PCLK_CORE_PRE_DIV_SHIFT, 191 192 /* CRU_CLK_SEL5_CON */ 193 ACLK_CORE_NIU2BUS_SEL_SHIFT = 14, 194 ACLK_CORE_NIU2BUS_SEL_MASK = 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT, 195 ACLK_CORE_NDFT_DIV_SHIFT = 8, 196 ACLK_CORE_NDFT_DIV_MASK = 0x1f << ACLK_CORE_NDFT_DIV_SHIFT, 197 198 /* CRU_CLK_SEL10_CON */ 199 HCLK_PERIMID_SEL_SHIFT = 6, 200 HCLK_PERIMID_SEL_MASK = 3 << HCLK_PERIMID_SEL_SHIFT, 201 HCLK_PERIMID_SEL_150M = 0, 202 HCLK_PERIMID_SEL_100M, 203 HCLK_PERIMID_SEL_75M, 204 HCLK_PERIMID_SEL_24M, 205 ACLK_PERIMID_SEL_SHIFT = 4, 206 ACLK_PERIMID_SEL_MASK = 3 << ACLK_PERIMID_SEL_SHIFT, 207 ACLK_PERIMID_SEL_300M = 0, 208 ACLK_PERIMID_SEL_200M, 209 ACLK_PERIMID_SEL_100M, 210 ACLK_PERIMID_SEL_24M, 211 212 /* CRU_CLK_SEL21_CON */ 213 I2S3_MCLKOUT_TX_SEL_SHIFT = 15, 214 I2S3_MCLKOUT_TX_SEL_MASK = 1 << I2S3_MCLKOUT_TX_SEL_SHIFT, 215 I2S3_MCLKOUT_TX_SEL_MCLK = 0, 216 I2S3_MCLKOUT_TX_SEL_12M, 217 CLK_I2S3_SEL_SHIFT = 10, 218 CLK_I2S3_SEL_MASK = 0x3 << CLK_I2S3_SEL_SHIFT, 219 CLK_I2S3_SEL_SRC = 0, 220 CLK_I2S3_SEL_FRAC, 221 CLK_I2S3_SEL_CLKIN, 222 CLK_I2S3_SEL_XIN12M, 223 CLK_I2S3_SRC_SEL_SHIFT = 8, 224 CLK_I2S3_SRC_SEL_MASK = 0x3 << CLK_I2S3_SRC_SEL_SHIFT, 225 CLK_I2S3_SRC_SEL_GPLL = 0, 226 CLK_I2S3_SRC_SEL_CPLL, 227 CLK_I2S3_SRC_SEL_NPLL, 228 CLK_I2S3_SRC_DIV_SHIFT = 0, 229 CLK_I2S3_SRC_DIV_MASK = 0x7f << CLK_I2S3_SRC_DIV_SHIFT, 230 231 /* CRU_CLK_SEL22_CON */ 232 CLK_I2S3_FRAC_NUMERATOR_SHIFT = 16, 233 CLK_I2S3_FRAC_NUMERATOR_MASK = 0xffff << 16, 234 CLK_I2S3_FRAC_DENOMINATOR_SHIFT = 0, 235 CLK_I2S3_FRAC_DENOMINATOR_MASK = 0xffff, 236 237 /* CRU_CLK_SEL27_CON */ 238 CLK_CRYPTO_PKA_SEL_SHIFT = 6, 239 CLK_CRYPTO_PKA_SEL_MASK = 3 << CLK_CRYPTO_PKA_SEL_SHIFT, 240 CLK_CRYPTO_PKA_SEL_300M = 0, 241 CLK_CRYPTO_PKA_SEL_200M, 242 CLK_CRYPTO_PKA_SEL_100M, 243 CLK_CRYPTO_CORE_SEL_SHIFT = 4, 244 CLK_CRYPTO_CORE_SEL_MASK = 3 << CLK_CRYPTO_CORE_SEL_SHIFT, 245 CLK_CRYPTO_CORE_SEL_200M = 0, 246 CLK_CRYPTO_CORE_SEL_150M, 247 CLK_CRYPTO_CORE_SEL_100M, 248 HCLK_SECURE_FLASH_SEL_SHIFT = 2, 249 HCLK_SECURE_FLASH_SEL_MASK = 3 << HCLK_SECURE_FLASH_SEL_SHIFT, 250 HCLK_SECURE_FLASH_SEL_150M = 0, 251 HCLK_SECURE_FLASH_SEL_100M, 252 HCLK_SECURE_FLASH_SEL_75M, 253 HCLK_SECURE_FLASH_SEL_24M, 254 ACLK_SECURE_FLASH_SEL_SHIFT = 0, 255 ACLK_SECURE_FLASH_SEL_MASK = 3 << ACLK_SECURE_FLASH_SEL_SHIFT, 256 ACLK_SECURE_FLASH_SEL_200M = 0, 257 ACLK_SECURE_FLASH_SEL_150M, 258 ACLK_SECURE_FLASH_SEL_100M, 259 ACLK_SECURE_FLASH_SEL_24M, 260 261 /* CRU_CLK_SEL28_CON */ 262 CCLK_EMMC_SEL_SHIFT = 12, 263 CCLK_EMMC_SEL_MASK = 7 << CCLK_EMMC_SEL_SHIFT, 264 CCLK_EMMC_SEL_24M = 0, 265 CCLK_EMMC_SEL_200M, 266 CCLK_EMMC_SEL_150M, 267 CCLK_EMMC_SEL_100M, 268 CCLK_EMMC_SEL_50M, 269 CCLK_EMMC_SEL_375K, 270 BCLK_EMMC_SEL_SHIFT = 8, 271 BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, 272 BCLK_EMMC_SEL_200M = 0, 273 BCLK_EMMC_SEL_150M, 274 BCLK_EMMC_SEL_125M, 275 SCLK_SFC_SEL_SHIFT = 4, 276 SCLK_SFC_SEL_MASK = 7 << SCLK_SFC_SEL_SHIFT, 277 SCLK_SFC_SEL_24M = 0, 278 SCLK_SFC_SEL_50M, 279 SCLK_SFC_SEL_75M, 280 SCLK_SFC_SEL_100M, 281 SCLK_SFC_SEL_125M, 282 SCLK_SFC_SEL_150M, 283 NCLK_NANDC_SEL_SHIFT = 0, 284 NCLK_NANDC_SEL_MASK = 3 << NCLK_NANDC_SEL_SHIFT, 285 NCLK_NANDC_SEL_200M = 0, 286 NCLK_NANDC_SEL_150M, 287 NCLK_NANDC_SEL_100M, 288 NCLK_NANDC_SEL_24M, 289 290 /* CRU_CLK_SEL30_CON */ 291 CLK_SDMMC1_SEL_SHIFT = 12, 292 CLK_SDMMC1_SEL_MASK = 7 << CLK_SDMMC1_SEL_SHIFT, 293 CLK_SDMMC0_SEL_SHIFT = 8, 294 CLK_SDMMC0_SEL_MASK = 7 << CLK_SDMMC0_SEL_SHIFT, 295 CLK_SDMMC_SEL_24M = 0, 296 CLK_SDMMC_SEL_400M, 297 CLK_SDMMC_SEL_300M, 298 CLK_SDMMC_SEL_100M, 299 CLK_SDMMC_SEL_50M, 300 CLK_SDMMC_SEL_750K, 301 302 /* CRU_CLK_SEL31_CON */ 303 CLK_MAC0_OUT_SEL_SHIFT = 14, 304 CLK_MAC0_OUT_SEL_MASK = 3 << CLK_MAC0_OUT_SEL_SHIFT, 305 CLK_MAC0_OUT_SEL_125M = 0, 306 CLK_MAC0_OUT_SEL_50M, 307 CLK_MAC0_OUT_SEL_25M, 308 CLK_MAC0_OUT_SEL_24M, 309 CLK_GMAC0_PTP_REF_SEL_SHIFT = 12, 310 CLK_GMAC0_PTP_REF_SEL_MASK = 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT, 311 CLK_GMAC0_PTP_REF_SEL_62_5M = 0, 312 CLK_GMAC0_PTP_REF_SEL_100M, 313 CLK_GMAC0_PTP_REF_SEL_50M, 314 CLK_GMAC0_PTP_REF_SEL_24M, 315 CLK_MAC0_2TOP_SEL_SHIFT = 8, 316 CLK_MAC0_2TOP_SEL_MASK = 3 << CLK_MAC0_2TOP_SEL_SHIFT, 317 CLK_MAC0_2TOP_SEL_125M = 0, 318 CLK_MAC0_2TOP_SEL_50M, 319 CLK_MAC0_2TOP_SEL_25M, 320 CLK_MAC0_2TOP_SEL_PPLL, 321 RGMII0_CLK_SEL_SHIFT = 4, 322 RGMII0_CLK_SEL_MASK = 3 << RGMII0_CLK_SEL_SHIFT, 323 RGMII0_CLK_SEL_125M = 0, 324 RGMII0_CLK_SEL_125M_1, 325 RGMII0_CLK_SEL_2_5M, 326 RGMII0_CLK_SEL_25M, 327 RMII0_CLK_SEL_SHIFT = 3, 328 RMII0_CLK_SEL_MASK = 1 << RMII0_CLK_SEL_SHIFT, 329 RMII0_CLK_SEL_2_5M = 0, 330 RMII0_CLK_SEL_25M, 331 RMII0_EXTCLK_SEL_SHIFT = 2, 332 RMII0_EXTCLK_SEL_MASK = 1 << RMII0_EXTCLK_SEL_SHIFT, 333 RMII0_EXTCLK_SEL_MAC0_TOP = 0, 334 RMII0_EXTCLK_SEL_IO, 335 RMII0_MODE_SHIFT = 0, 336 RMII0_MODE_MASK = 3 << RMII0_MODE_SHIFT, 337 RMII0_MODE_SEL_RGMII = 0, 338 RMII0_MODE_SEL_RMII, 339 RMII0_MODE_SEL_GMII, 340 341 /* CRU_CLK_SEL32_CON */ 342 CLK_SDMMC2_SEL_SHIFT = 8, 343 CLK_SDMMC2_SEL_MASK = 7 << CLK_SDMMC2_SEL_SHIFT, 344 345 /* CRU_CLK_SEL38_CON */ 346 ACLK_VOP_PRE_SEL_SHIFT = 6, 347 ACLK_VOP_PRE_SEL_MASK = 3 << ACLK_VOP_PRE_SEL_SHIFT, 348 ACLK_VOP_PRE_SEL_CPLL = 0, 349 ACLK_VOP_PRE_SEL_GPLL, 350 ACLK_VOP_PRE_SEL_HPLL, 351 ACLK_VOP_PRE_SEL_VPLL, 352 ACLK_VOP_PRE_DIV_SHIFT = 0, 353 ACLK_VOP_PRE_DIV_MASK = 0x1f << ACLK_VOP_PRE_DIV_SHIFT, 354 355 /* CRU_CLK_SEL39_CON */ 356 DCLK0_VOP_SEL_SHIFT = 10, 357 DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT, 358 DCLK_VOP_SEL_HPLL = 0, 359 DCLK_VOP_SEL_VPLL, 360 DCLK_VOP_SEL_GPLL, 361 DCLK_VOP_SEL_CPLL, 362 DCLK0_VOP_DIV_SHIFT = 0, 363 DCLK0_VOP_DIV_MASK = 0xff << DCLK0_VOP_DIV_SHIFT, 364 365 /* CRU_CLK_SEL40_CON */ 366 DCLK1_VOP_SEL_SHIFT = 10, 367 DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT, 368 DCLK1_VOP_DIV_SHIFT = 0, 369 DCLK1_VOP_DIV_MASK = 0xff << DCLK1_VOP_DIV_SHIFT, 370 371 /* CRU_CLK_SEL41_CON */ 372 DCLK2_VOP_SEL_SHIFT = 10, 373 DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT, 374 DCLK2_VOP_DIV_SHIFT = 0, 375 DCLK2_VOP_DIV_MASK = 0xff << DCLK2_VOP_DIV_SHIFT, 376 377 /* CRU_CLK_SEL43_CON */ 378 DCLK_EBC_SEL_SHIFT = 6, 379 DCLK_EBC_SEL_MASK = 3 << DCLK_EBC_SEL_SHIFT, 380 DCLK_EBC_SEL_GPLL_400M = 0, 381 DCLK_EBC_SEL_CPLL_333M, 382 DCLK_EBC_SEL_GPLL_200M, 383 384 /* CRU_CLK_SEL47_CON */ 385 ACLK_RKVDEC_SEL_SHIFT = 7, 386 ACLK_RKVDEC_SEL_MASK = 1 << ACLK_RKVDEC_SEL_SHIFT, 387 ACLK_RKVDEC_SEL_GPLL = 0, 388 ACLK_RKVDEC_SEL_CPLL, 389 ACLK_RKVDEC_DIV_SHIFT = 0, 390 ACLK_RKVDEC_DIV_MASK = 0x1f << ACLK_RKVDEC_DIV_SHIFT, 391 392 /* CRU_CLK_SEL49_CON */ 393 CLK_RKVDEC_CORE_SEL_SHIFT = 14, 394 CLK_RKVDEC_CORE_SEL_MASK = 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT, 395 CLK_RKVDEC_CORE_SEL_GPLL = 0, 396 CLK_RKVDEC_CORE_SEL_CPLL, 397 CLK_RKVDEC_CORE_SEL_NPLL, 398 CLK_RKVDEC_CORE_SEL_VPLL, 399 CLK_RKVDEC_CORE_DIV_SHIFT = 8, 400 CLK_RKVDEC_CORE_DIV_MASK = 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT, 401 402 /* CRU_CLK_SEL50_CON */ 403 PCLK_BUS_SEL_SHIFT = 4, 404 PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT, 405 PCLK_BUS_SEL_100M = 0, 406 PCLK_BUS_SEL_75M, 407 PCLK_BUS_SEL_50M, 408 PCLK_BUS_SEL_24M, 409 ACLK_BUS_SEL_SHIFT = 0, 410 ACLK_BUS_SEL_MASK = 3 << ACLK_BUS_SEL_SHIFT, 411 ACLK_BUS_SEL_200M = 0, 412 ACLK_BUS_SEL_150M, 413 ACLK_BUS_SEL_100M, 414 ACLK_BUS_SEL_24M, 415 416 /* CRU_CLK_SEL51_CON */ 417 CLK_TSADC_DIV_SHIFT = 8, 418 CLK_TSADC_DIV_MASK = 0x7f << CLK_TSADC_DIV_SHIFT, 419 CLK_TSADC_TSEN_SEL_SHIFT = 4, 420 CLK_TSADC_TSEN_SEL_MASK = 0x3 << CLK_TSADC_TSEN_SEL_SHIFT, 421 CLK_TSADC_TSEN_SEL_24M = 0, 422 CLK_TSADC_TSEN_SEL_100M, 423 CLK_TSADC_TSEN_SEL_CPLL_100M, 424 CLK_TSADC_TSEN_DIV_SHIFT = 0, 425 CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT, 426 427 /* CRU_CLK_SEL52_CON */ 428 CLK_UART_SEL_SHIFT = 12, 429 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 430 CLK_UART_SEL_SRC = 0, 431 CLK_UART_SEL_FRAC, 432 CLK_UART_SEL_XIN24M, 433 CLK_UART_SRC_SEL_SHIFT = 8, 434 CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, 435 CLK_UART_SRC_SEL_GPLL = 0, 436 CLK_UART_SRC_SEL_CPLL, 437 CLK_UART_SRC_SEL_480M, 438 CLK_UART_SRC_DIV_SHIFT = 0, 439 CLK_UART_SRC_DIV_MASK = 0x3f << CLK_UART_SRC_DIV_SHIFT, 440 441 /* CRU_CLK_SEL53_CON */ 442 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 443 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 444 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 445 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 446 447 /* CRU_CLK_SEL71_CON */ 448 CLK_I2C_SEL_SHIFT = 8, 449 CLK_I2C_SEL_MASK = 3 << CLK_I2C_SEL_SHIFT, 450 CLK_I2C_SEL_200M = 0, 451 CLK_I2C_SEL_100M, 452 CLK_I2C_SEL_24M, 453 CLK_I2C_SEL_CPLL_100M, 454 455 /* CRU_CLK_SEL72_CON */ 456 CLK_PWM3_SEL_SHIFT = 12, 457 CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT, 458 CLK_PWM2_SEL_SHIFT = 10, 459 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, 460 CLK_PWM1_SEL_SHIFT = 8, 461 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, 462 CLK_PWM_SEL_100M = 0, 463 CLK_PWM_SEL_24M, 464 CLK_PWM_SEL_CPLL_100M, 465 CLK_SPI3_SEL_SHIFT = 6, 466 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, 467 CLK_SPI2_SEL_SHIFT = 4, 468 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, 469 CLK_SPI1_SEL_SHIFT = 2, 470 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, 471 CLK_SPI0_SEL_SHIFT = 0, 472 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 473 CLK_SPI_SEL_200M = 0, 474 CLK_SPI_SEL_24M, 475 CLK_SPI_SEL_CPLL_100M, 476 477 /* CRU_CLK_SEL73_CON */ 478 PCLK_TOP_SEL_SHIFT = 12, 479 PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, 480 PCLK_TOP_SEL_100M = 0, 481 PCLK_TOP_SEL_75M, 482 PCLK_TOP_SEL_50M, 483 PCLK_TOP_SEL_24M, 484 HCLK_TOP_SEL_SHIFT = 8, 485 HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, 486 HCLK_TOP_SEL_150M = 0, 487 HCLK_TOP_SEL_100M, 488 HCLK_TOP_SEL_75M, 489 HCLK_TOP_SEL_24M, 490 ACLK_TOP_LOW_SEL_SHIFT = 4, 491 ACLK_TOP_LOW_SEL_MASK = 3 << ACLK_TOP_LOW_SEL_SHIFT, 492 ACLK_TOP_LOW_SEL_400M = 0, 493 ACLK_TOP_LOW_SEL_300M, 494 ACLK_TOP_LOW_SEL_200M, 495 ACLK_TOP_LOW_SEL_24M, 496 ACLK_TOP_HIGH_SEL_SHIFT = 0, 497 ACLK_TOP_HIGH_SEL_MASK = 3 << ACLK_TOP_HIGH_SEL_SHIFT, 498 ACLK_TOP_HIGH_SEL_500M = 0, 499 ACLK_TOP_HIGH_SEL_400M, 500 ACLK_TOP_HIGH_SEL_300M, 501 ACLK_TOP_HIGH_SEL_24M, 502 503 /* CRU_CLK_SEL78_CON */ 504 CPLL_500M_DIV_SHIFT = 8, 505 CPLL_500M_DIV_MASK = 0x1f << CPLL_500M_DIV_SHIFT, 506 507 /* CRU_CLK_SEL79_CON */ 508 CPLL_250M_DIV_SHIFT = 8, 509 CPLL_250M_DIV_MASK = 0x1f << CPLL_250M_DIV_SHIFT, 510 CPLL_333M_DIV_SHIFT = 0, 511 CPLL_333M_DIV_MASK = 0x1f << CPLL_333M_DIV_SHIFT, 512 513 /* CRU_CLK_SEL80_CON */ 514 CPLL_62P5M_DIV_SHIFT = 8, 515 CPLL_62P5M_DIV_MASK = 0x1f << CPLL_62P5M_DIV_SHIFT, 516 CPLL_125M_DIV_SHIFT = 0, 517 CPLL_125M_DIV_MASK = 0x1f << CPLL_125M_DIV_SHIFT, 518 519 /* CRU_CLK_SEL81_CON */ 520 CPLL_25M_DIV_SHIFT = 8, 521 CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT, 522 CPLL_50M_DIV_SHIFT = 0, 523 CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT, 524 525 /* CRU_CLK_SEL82_CON */ 526 CPLL_100M_DIV_SHIFT = 0, 527 CPLL_100M_DIV_MASK = 0x1f << CPLL_100M_DIV_SHIFT, 528 529 /* GRF_SOC_CON2 */ 530 I2S3_MCLKOUT_SEL_SHIFT = 15, 531 I2S3_MCLKOUT_SEL_MASK = 0x1 << I2S3_MCLKOUT_SEL_SHIFT, 532 I2S3_MCLKOUT_SEL_RX = 0, 533 I2S3_MCLKOUT_SEL_TX, 534 I2S3_MCLK_IOE_SEL_SHIFT = 3, 535 I2S3_MCLK_IOE_SEL_MASK = 0x1 << I2S3_MCLK_IOE_SEL_SHIFT, 536 I2S3_MCLK_IOE_SEL_CLKIN = 0, 537 I2S3_MCLK_IOE_SEL_CLKOUT, 538 539 }; 540 #endif 541