Home
last modified time | relevance | path

Searched refs:CLK_TOP_AXI_SEL (Results 1 – 18 of 18) sorted by relevance

/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmt7629.dtsi268 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
320 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
383 <&topckgen CLK_TOP_AXI_SEL>,
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt8135-clk.h73 #define CLK_TOP_AXI_SEL 62 macro
H A Dmt7629-clk.h83 #define CLK_TOP_AXI_SEL 73 macro
H A Dmt7622-clk.h68 #define CLK_TOP_AXI_SEL 56 macro
H A Dmt6765-clk.h131 #define CLK_TOP_AXI_SEL 96 macro
H A Dmt8173-clk.h92 #define CLK_TOP_AXI_SEL 82 macro
H A Dmt2712-clk.h130 #define CLK_TOP_AXI_SEL 99 macro
H A Dmt2701-clk.h90 #define CLK_TOP_AXI_SEL 79 macro
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt7629.c487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
593 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
H A Dclk-mt7622.c515 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
639 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
H A Dclk-mt8135.c352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt2701.c488 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt8173.c542 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
H A Dclk-mt6765.c367 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
H A Dclk-mt2712.c738 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi252 <&topckgen CLK_TOP_AXI_SEL>;
699 <&topckgen CLK_TOP_AXI_SEL>;
H A Dmt2712e.dtsi774 <&topckgen CLK_TOP_AXI_SEL>,
785 <&topckgen CLK_TOP_AXI_SEL>,
H A Dmt8173.dtsi837 <&topckgen CLK_TOP_AXI_SEL>;
847 <&topckgen CLK_TOP_AXI_SEL>;