1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc. 4*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT8173_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT8173_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* TOPCKGEN */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_TOP_CLKPH_MCK_O 1 13*4882a593Smuzhiyun #define CLK_TOP_USB_SYSPLL_125M 3 14*4882a593Smuzhiyun #define CLK_TOP_HDMITX_DIG_CTS 4 15*4882a593Smuzhiyun #define CLK_TOP_ARMCA7PLL_754M 5 16*4882a593Smuzhiyun #define CLK_TOP_ARMCA7PLL_502M 6 17*4882a593Smuzhiyun #define CLK_TOP_MAIN_H546M 7 18*4882a593Smuzhiyun #define CLK_TOP_MAIN_H364M 8 19*4882a593Smuzhiyun #define CLK_TOP_MAIN_H218P4M 9 20*4882a593Smuzhiyun #define CLK_TOP_MAIN_H156M 10 21*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_445P5M 11 22*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_594M 12 23*4882a593Smuzhiyun #define CLK_TOP_UNIV_624M 13 24*4882a593Smuzhiyun #define CLK_TOP_UNIV_416M 14 25*4882a593Smuzhiyun #define CLK_TOP_UNIV_249P6M 15 26*4882a593Smuzhiyun #define CLK_TOP_UNIV_178P3M 16 27*4882a593Smuzhiyun #define CLK_TOP_UNIV_48M 17 28*4882a593Smuzhiyun #define CLK_TOP_CLKRTC_EXT 18 29*4882a593Smuzhiyun #define CLK_TOP_CLKRTC_INT 19 30*4882a593Smuzhiyun #define CLK_TOP_FPC 20 31*4882a593Smuzhiyun #define CLK_TOP_HDMITXPLL_D2 21 32*4882a593Smuzhiyun #define CLK_TOP_HDMITXPLL_D3 22 33*4882a593Smuzhiyun #define CLK_TOP_ARMCA7PLL_D2 23 34*4882a593Smuzhiyun #define CLK_TOP_ARMCA7PLL_D3 24 35*4882a593Smuzhiyun #define CLK_TOP_APLL1 25 36*4882a593Smuzhiyun #define CLK_TOP_APLL2 26 37*4882a593Smuzhiyun #define CLK_TOP_DMPLL 27 38*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D2 28 39*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D4 29 40*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D8 30 41*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D16 31 42*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D2 32 43*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D4 33 44*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D8 34 45*4882a593Smuzhiyun #define CLK_TOP_MMPLL 35 46*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D2 36 47*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL 37 48*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D2 38 49*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D4 39 50*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL2 40 51*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL2_D2 41 52*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL2_D4 42 53*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 43 54*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D2 44 55*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D4 45 56*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D8 46 57*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D16 47 58*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3 48 59*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D2 49 60*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D4 50 61*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 51 62*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D2 52 63*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D4 53 64*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7 54 65*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D2 55 66*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D4 56 67*4882a593Smuzhiyun #define CLK_TOP_TVDPLL 57 68*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D2 58 69*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D4 59 70*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D8 60 71*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D16 61 72*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 62 73*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 63 74*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 64 75*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D8 65 76*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 66 77*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 67 78*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 68 79*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 69 80*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 70 81*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D2 71 82*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D4 72 83*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D8 73 84*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 74 85*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D26 75 86*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D52 76 87*4882a593Smuzhiyun #define CLK_TOP_VCODECPLL 77 88*4882a593Smuzhiyun #define CLK_TOP_VCODECPLL_370P5 78 89*4882a593Smuzhiyun #define CLK_TOP_VENCPLL 79 90*4882a593Smuzhiyun #define CLK_TOP_VENCPLL_D2 80 91*4882a593Smuzhiyun #define CLK_TOP_VENCPLL_D4 81 92*4882a593Smuzhiyun #define CLK_TOP_AXI_SEL 82 93*4882a593Smuzhiyun #define CLK_TOP_MEM_SEL 83 94*4882a593Smuzhiyun #define CLK_TOP_DDRPHYCFG_SEL 84 95*4882a593Smuzhiyun #define CLK_TOP_MM_SEL 85 96*4882a593Smuzhiyun #define CLK_TOP_PWM_SEL 86 97*4882a593Smuzhiyun #define CLK_TOP_VDEC_SEL 87 98*4882a593Smuzhiyun #define CLK_TOP_VENC_SEL 88 99*4882a593Smuzhiyun #define CLK_TOP_MFG_SEL 89 100*4882a593Smuzhiyun #define CLK_TOP_CAMTG_SEL 90 101*4882a593Smuzhiyun #define CLK_TOP_UART_SEL 91 102*4882a593Smuzhiyun #define CLK_TOP_SPI_SEL 92 103*4882a593Smuzhiyun #define CLK_TOP_USB20_SEL 93 104*4882a593Smuzhiyun #define CLK_TOP_USB30_SEL 94 105*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_H_SEL 95 106*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_SEL 96 107*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1_SEL 97 108*4882a593Smuzhiyun #define CLK_TOP_MSDC30_2_SEL 98 109*4882a593Smuzhiyun #define CLK_TOP_MSDC30_3_SEL 99 110*4882a593Smuzhiyun #define CLK_TOP_AUDIO_SEL 100 111*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS_SEL 101 112*4882a593Smuzhiyun #define CLK_TOP_PMICSPI_SEL 102 113*4882a593Smuzhiyun #define CLK_TOP_SCP_SEL 103 114*4882a593Smuzhiyun #define CLK_TOP_ATB_SEL 104 115*4882a593Smuzhiyun #define CLK_TOP_VENC_LT_SEL 105 116*4882a593Smuzhiyun #define CLK_TOP_DPI0_SEL 106 117*4882a593Smuzhiyun #define CLK_TOP_IRDA_SEL 107 118*4882a593Smuzhiyun #define CLK_TOP_CCI400_SEL 108 119*4882a593Smuzhiyun #define CLK_TOP_AUD_1_SEL 109 120*4882a593Smuzhiyun #define CLK_TOP_AUD_2_SEL 110 121*4882a593Smuzhiyun #define CLK_TOP_MEM_MFG_IN_SEL 111 122*4882a593Smuzhiyun #define CLK_TOP_AXI_MFG_IN_SEL 112 123*4882a593Smuzhiyun #define CLK_TOP_SCAM_SEL 113 124*4882a593Smuzhiyun #define CLK_TOP_SPINFI_IFR_SEL 114 125*4882a593Smuzhiyun #define CLK_TOP_HDMI_SEL 115 126*4882a593Smuzhiyun #define CLK_TOP_DPILVDS_SEL 116 127*4882a593Smuzhiyun #define CLK_TOP_MSDC50_2_H_SEL 117 128*4882a593Smuzhiyun #define CLK_TOP_HDCP_SEL 118 129*4882a593Smuzhiyun #define CLK_TOP_HDCP_24M_SEL 119 130*4882a593Smuzhiyun #define CLK_TOP_RTC_SEL 120 131*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV0 121 132*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV1 122 133*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV2 123 134*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV3 124 135*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV4 125 136*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV5 126 137*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV0 127 138*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV1 128 139*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV2 129 140*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV3 130 141*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV4 131 142*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV5 132 143*4882a593Smuzhiyun #define CLK_TOP_I2S0_M_SEL 133 144*4882a593Smuzhiyun #define CLK_TOP_I2S1_M_SEL 134 145*4882a593Smuzhiyun #define CLK_TOP_I2S2_M_SEL 135 146*4882a593Smuzhiyun #define CLK_TOP_I2S3_M_SEL 136 147*4882a593Smuzhiyun #define CLK_TOP_I2S3_B_SEL 137 148*4882a593Smuzhiyun #define CLK_TOP_DSI0_DIG 138 149*4882a593Smuzhiyun #define CLK_TOP_DSI1_DIG 139 150*4882a593Smuzhiyun #define CLK_TOP_LVDS_PXL 140 151*4882a593Smuzhiyun #define CLK_TOP_LVDS_CTS 141 152*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 142 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* APMIXED_SYS */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define CLK_APMIXED_ARMCA15PLL 1 157*4882a593Smuzhiyun #define CLK_APMIXED_ARMCA7PLL 2 158*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 3 159*4882a593Smuzhiyun #define CLK_APMIXED_UNIVPLL 4 160*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 5 161*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 6 162*4882a593Smuzhiyun #define CLK_APMIXED_VENCPLL 7 163*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL 8 164*4882a593Smuzhiyun #define CLK_APMIXED_MPLL 9 165*4882a593Smuzhiyun #define CLK_APMIXED_VCODECPLL 10 166*4882a593Smuzhiyun #define CLK_APMIXED_APLL1 11 167*4882a593Smuzhiyun #define CLK_APMIXED_APLL2 12 168*4882a593Smuzhiyun #define CLK_APMIXED_LVDSPLL 13 169*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL2 14 170*4882a593Smuzhiyun #define CLK_APMIXED_REF2USB_TX 15 171*4882a593Smuzhiyun #define CLK_APMIXED_HDMI_REF 16 172*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 17 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /* INFRA_SYS */ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define CLK_INFRA_DBGCLK 1 177*4882a593Smuzhiyun #define CLK_INFRA_SMI 2 178*4882a593Smuzhiyun #define CLK_INFRA_AUDIO 3 179*4882a593Smuzhiyun #define CLK_INFRA_GCE 4 180*4882a593Smuzhiyun #define CLK_INFRA_L2C_SRAM 5 181*4882a593Smuzhiyun #define CLK_INFRA_M4U 6 182*4882a593Smuzhiyun #define CLK_INFRA_CPUM 7 183*4882a593Smuzhiyun #define CLK_INFRA_KP 8 184*4882a593Smuzhiyun #define CLK_INFRA_CEC 9 185*4882a593Smuzhiyun #define CLK_INFRA_PMICSPI 10 186*4882a593Smuzhiyun #define CLK_INFRA_PMICWRAP 11 187*4882a593Smuzhiyun #define CLK_INFRA_CLK_13M 12 188*4882a593Smuzhiyun #define CLK_INFRA_CA53SEL 13 189*4882a593Smuzhiyun #define CLK_INFRA_CA57SEL 14 /* Deprecated. Don't use it. */ 190*4882a593Smuzhiyun #define CLK_INFRA_CA72SEL 14 191*4882a593Smuzhiyun #define CLK_INFRA_NR_CLK 15 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* PERI_SYS */ 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define CLK_PERI_NFI 1 196*4882a593Smuzhiyun #define CLK_PERI_THERM 2 197*4882a593Smuzhiyun #define CLK_PERI_PWM1 3 198*4882a593Smuzhiyun #define CLK_PERI_PWM2 4 199*4882a593Smuzhiyun #define CLK_PERI_PWM3 5 200*4882a593Smuzhiyun #define CLK_PERI_PWM4 6 201*4882a593Smuzhiyun #define CLK_PERI_PWM5 7 202*4882a593Smuzhiyun #define CLK_PERI_PWM6 8 203*4882a593Smuzhiyun #define CLK_PERI_PWM7 9 204*4882a593Smuzhiyun #define CLK_PERI_PWM 10 205*4882a593Smuzhiyun #define CLK_PERI_USB0 11 206*4882a593Smuzhiyun #define CLK_PERI_USB1 12 207*4882a593Smuzhiyun #define CLK_PERI_AP_DMA 13 208*4882a593Smuzhiyun #define CLK_PERI_MSDC30_0 14 209*4882a593Smuzhiyun #define CLK_PERI_MSDC30_1 15 210*4882a593Smuzhiyun #define CLK_PERI_MSDC30_2 16 211*4882a593Smuzhiyun #define CLK_PERI_MSDC30_3 17 212*4882a593Smuzhiyun #define CLK_PERI_NLI_ARB 18 213*4882a593Smuzhiyun #define CLK_PERI_IRDA 19 214*4882a593Smuzhiyun #define CLK_PERI_UART0 20 215*4882a593Smuzhiyun #define CLK_PERI_UART1 21 216*4882a593Smuzhiyun #define CLK_PERI_UART2 22 217*4882a593Smuzhiyun #define CLK_PERI_UART3 23 218*4882a593Smuzhiyun #define CLK_PERI_I2C0 24 219*4882a593Smuzhiyun #define CLK_PERI_I2C1 25 220*4882a593Smuzhiyun #define CLK_PERI_I2C2 26 221*4882a593Smuzhiyun #define CLK_PERI_I2C3 27 222*4882a593Smuzhiyun #define CLK_PERI_I2C4 28 223*4882a593Smuzhiyun #define CLK_PERI_AUXADC 29 224*4882a593Smuzhiyun #define CLK_PERI_SPI0 30 225*4882a593Smuzhiyun #define CLK_PERI_I2C5 31 226*4882a593Smuzhiyun #define CLK_PERI_NFIECC 32 227*4882a593Smuzhiyun #define CLK_PERI_SPI 33 228*4882a593Smuzhiyun #define CLK_PERI_IRRX 34 229*4882a593Smuzhiyun #define CLK_PERI_I2C6 35 230*4882a593Smuzhiyun #define CLK_PERI_UART0_SEL 36 231*4882a593Smuzhiyun #define CLK_PERI_UART1_SEL 37 232*4882a593Smuzhiyun #define CLK_PERI_UART2_SEL 38 233*4882a593Smuzhiyun #define CLK_PERI_UART3_SEL 39 234*4882a593Smuzhiyun #define CLK_PERI_NR_CLK 40 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* IMG_SYS */ 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun #define CLK_IMG_LARB2_SMI 1 239*4882a593Smuzhiyun #define CLK_IMG_CAM_SMI 2 240*4882a593Smuzhiyun #define CLK_IMG_CAM_CAM 3 241*4882a593Smuzhiyun #define CLK_IMG_SEN_TG 4 242*4882a593Smuzhiyun #define CLK_IMG_SEN_CAM 5 243*4882a593Smuzhiyun #define CLK_IMG_CAM_SV 6 244*4882a593Smuzhiyun #define CLK_IMG_FD 7 245*4882a593Smuzhiyun #define CLK_IMG_NR_CLK 8 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* MM_SYS */ 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 1 250*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 2 251*4882a593Smuzhiyun #define CLK_MM_CAM_MDP 3 252*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA0 4 253*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA1 5 254*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 6 255*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 7 256*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ2 8 257*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP0 9 258*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP1 10 259*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA 11 260*4882a593Smuzhiyun #define CLK_MM_MDP_WROT0 12 261*4882a593Smuzhiyun #define CLK_MM_MDP_WROT1 13 262*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 14 263*4882a593Smuzhiyun #define CLK_MM_MUTEX_32K 15 264*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0 16 265*4882a593Smuzhiyun #define CLK_MM_DISP_OVL1 17 266*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA0 18 267*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA1 19 268*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA2 20 269*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA0 21 270*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA1 22 271*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR0 23 272*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR1 24 273*4882a593Smuzhiyun #define CLK_MM_DISP_AAL 25 274*4882a593Smuzhiyun #define CLK_MM_DISP_GAMMA 26 275*4882a593Smuzhiyun #define CLK_MM_DISP_UFOE 27 276*4882a593Smuzhiyun #define CLK_MM_DISP_SPLIT0 28 277*4882a593Smuzhiyun #define CLK_MM_DISP_SPLIT1 29 278*4882a593Smuzhiyun #define CLK_MM_DISP_MERGE 30 279*4882a593Smuzhiyun #define CLK_MM_DISP_OD 31 280*4882a593Smuzhiyun #define CLK_MM_DISP_PWM0MM 32 281*4882a593Smuzhiyun #define CLK_MM_DISP_PWM026M 33 282*4882a593Smuzhiyun #define CLK_MM_DISP_PWM1MM 34 283*4882a593Smuzhiyun #define CLK_MM_DISP_PWM126M 35 284*4882a593Smuzhiyun #define CLK_MM_DSI0_ENGINE 36 285*4882a593Smuzhiyun #define CLK_MM_DSI0_DIGITAL 37 286*4882a593Smuzhiyun #define CLK_MM_DSI1_ENGINE 38 287*4882a593Smuzhiyun #define CLK_MM_DSI1_DIGITAL 39 288*4882a593Smuzhiyun #define CLK_MM_DPI_PIXEL 40 289*4882a593Smuzhiyun #define CLK_MM_DPI_ENGINE 41 290*4882a593Smuzhiyun #define CLK_MM_DPI1_PIXEL 42 291*4882a593Smuzhiyun #define CLK_MM_DPI1_ENGINE 43 292*4882a593Smuzhiyun #define CLK_MM_HDMI_PIXEL 44 293*4882a593Smuzhiyun #define CLK_MM_HDMI_PLLCK 45 294*4882a593Smuzhiyun #define CLK_MM_HDMI_AUDIO 46 295*4882a593Smuzhiyun #define CLK_MM_HDMI_SPDIF 47 296*4882a593Smuzhiyun #define CLK_MM_LVDS_PIXEL 48 297*4882a593Smuzhiyun #define CLK_MM_LVDS_CTS 49 298*4882a593Smuzhiyun #define CLK_MM_SMI_LARB4 50 299*4882a593Smuzhiyun #define CLK_MM_HDMI_HDCP 51 300*4882a593Smuzhiyun #define CLK_MM_HDMI_HDCP24M 52 301*4882a593Smuzhiyun #define CLK_MM_NR_CLK 53 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun /* VDEC_SYS */ 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun #define CLK_VDEC_CKEN 1 306*4882a593Smuzhiyun #define CLK_VDEC_LARB_CKEN 2 307*4882a593Smuzhiyun #define CLK_VDEC_NR_CLK 3 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun /* VENC_SYS */ 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun #define CLK_VENC_CKE0 1 312*4882a593Smuzhiyun #define CLK_VENC_CKE1 2 313*4882a593Smuzhiyun #define CLK_VENC_CKE2 3 314*4882a593Smuzhiyun #define CLK_VENC_CKE3 4 315*4882a593Smuzhiyun #define CLK_VENC_NR_CLK 5 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* VENCLT_SYS */ 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #define CLK_VENCLT_CKE0 1 320*4882a593Smuzhiyun #define CLK_VENCLT_CKE1 2 321*4882a593Smuzhiyun #define CLK_VENCLT_NR_CLK 3 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT8173_H */ 324