1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT2712_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT2712_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* APMIXEDSYS */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 0 13*4882a593Smuzhiyun #define CLK_APMIXED_UNIVPLL 1 14*4882a593Smuzhiyun #define CLK_APMIXED_VCODECPLL 2 15*4882a593Smuzhiyun #define CLK_APMIXED_VENCPLL 3 16*4882a593Smuzhiyun #define CLK_APMIXED_APLL1 4 17*4882a593Smuzhiyun #define CLK_APMIXED_APLL2 5 18*4882a593Smuzhiyun #define CLK_APMIXED_LVDSPLL 6 19*4882a593Smuzhiyun #define CLK_APMIXED_LVDSPLL2 7 20*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 8 21*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL2 9 22*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL 10 23*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 11 24*4882a593Smuzhiyun #define CLK_APMIXED_ARMCA35PLL 12 25*4882a593Smuzhiyun #define CLK_APMIXED_ARMCA72PLL 13 26*4882a593Smuzhiyun #define CLK_APMIXED_ETHERPLL 14 27*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 15 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* TOPCKGEN */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CLK_TOP_ARMCA35PLL 0 32*4882a593Smuzhiyun #define CLK_TOP_ARMCA35PLL_600M 1 33*4882a593Smuzhiyun #define CLK_TOP_ARMCA35PLL_400M 2 34*4882a593Smuzhiyun #define CLK_TOP_ARMCA72PLL 3 35*4882a593Smuzhiyun #define CLK_TOP_SYSPLL 4 36*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 5 37*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D2 6 38*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D4 7 39*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D8 8 40*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D16 9 41*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3 10 42*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D2 11 43*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D4 12 44*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 13 45*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D2 14 46*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D4 15 47*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7 16 48*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D2 17 49*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D4 18 50*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL 19 51*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 20 52*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D26 21 53*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D52 22 54*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D104 23 55*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D208 24 56*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 25 57*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 26 58*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 27 59*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D8 28 60*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 29 61*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 30 62*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 31 63*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 32 64*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 33 65*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D2 34 66*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D4 35 67*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D8 36 68*4882a593Smuzhiyun #define CLK_TOP_F_MP0_PLL1 37 69*4882a593Smuzhiyun #define CLK_TOP_F_MP0_PLL2 38 70*4882a593Smuzhiyun #define CLK_TOP_F_BIG_PLL1 39 71*4882a593Smuzhiyun #define CLK_TOP_F_BIG_PLL2 40 72*4882a593Smuzhiyun #define CLK_TOP_F_BUS_PLL1 41 73*4882a593Smuzhiyun #define CLK_TOP_F_BUS_PLL2 42 74*4882a593Smuzhiyun #define CLK_TOP_APLL1 43 75*4882a593Smuzhiyun #define CLK_TOP_APLL1_D2 44 76*4882a593Smuzhiyun #define CLK_TOP_APLL1_D4 45 77*4882a593Smuzhiyun #define CLK_TOP_APLL1_D8 46 78*4882a593Smuzhiyun #define CLK_TOP_APLL1_D16 47 79*4882a593Smuzhiyun #define CLK_TOP_APLL2 48 80*4882a593Smuzhiyun #define CLK_TOP_APLL2_D2 49 81*4882a593Smuzhiyun #define CLK_TOP_APLL2_D4 50 82*4882a593Smuzhiyun #define CLK_TOP_APLL2_D8 51 83*4882a593Smuzhiyun #define CLK_TOP_APLL2_D16 52 84*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL 53 85*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D2 54 86*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D4 55 87*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D8 56 88*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL2 57 89*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL2_D2 58 90*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL2_D4 59 91*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL2_D8 60 92*4882a593Smuzhiyun #define CLK_TOP_ETHERPLL_125M 61 93*4882a593Smuzhiyun #define CLK_TOP_ETHERPLL_50M 62 94*4882a593Smuzhiyun #define CLK_TOP_CVBS 63 95*4882a593Smuzhiyun #define CLK_TOP_CVBS_D2 64 96*4882a593Smuzhiyun #define CLK_TOP_SYS_26M 65 97*4882a593Smuzhiyun #define CLK_TOP_MMPLL 66 98*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D2 67 99*4882a593Smuzhiyun #define CLK_TOP_VENCPLL 68 100*4882a593Smuzhiyun #define CLK_TOP_VENCPLL_D2 69 101*4882a593Smuzhiyun #define CLK_TOP_VCODECPLL 70 102*4882a593Smuzhiyun #define CLK_TOP_VCODECPLL_D2 71 103*4882a593Smuzhiyun #define CLK_TOP_TVDPLL 72 104*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D2 73 105*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D4 74 106*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D8 75 107*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_429M 76 108*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_429M_D2 77 109*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_429M_D4 78 110*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL 79 111*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D2 80 112*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D4 81 113*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL2 82 114*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL2_D2 83 115*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL2_D4 84 116*4882a593Smuzhiyun #define CLK_TOP_CLK26M_D2 85 117*4882a593Smuzhiyun #define CLK_TOP_D2A_ULCLK_6P5M 86 118*4882a593Smuzhiyun #define CLK_TOP_VPLL3_DPIX 87 119*4882a593Smuzhiyun #define CLK_TOP_VPLL_DPIX 88 120*4882a593Smuzhiyun #define CLK_TOP_LTEPLL_FS26M 89 121*4882a593Smuzhiyun #define CLK_TOP_DMPLL 90 122*4882a593Smuzhiyun #define CLK_TOP_DSI0_LNTC 91 123*4882a593Smuzhiyun #define CLK_TOP_DSI1_LNTC 92 124*4882a593Smuzhiyun #define CLK_TOP_LVDSTX3_CLKDIG_CTS 93 125*4882a593Smuzhiyun #define CLK_TOP_LVDSTX_CLKDIG_CTS 94 126*4882a593Smuzhiyun #define CLK_TOP_CLKRTC_EXT 95 127*4882a593Smuzhiyun #define CLK_TOP_CLKRTC_INT 96 128*4882a593Smuzhiyun #define CLK_TOP_CSI0 97 129*4882a593Smuzhiyun #define CLK_TOP_CVBSPLL 98 130*4882a593Smuzhiyun #define CLK_TOP_AXI_SEL 99 131*4882a593Smuzhiyun #define CLK_TOP_MEM_SEL 100 132*4882a593Smuzhiyun #define CLK_TOP_MM_SEL 101 133*4882a593Smuzhiyun #define CLK_TOP_PWM_SEL 102 134*4882a593Smuzhiyun #define CLK_TOP_VDEC_SEL 103 135*4882a593Smuzhiyun #define CLK_TOP_VENC_SEL 104 136*4882a593Smuzhiyun #define CLK_TOP_MFG_SEL 105 137*4882a593Smuzhiyun #define CLK_TOP_CAMTG_SEL 106 138*4882a593Smuzhiyun #define CLK_TOP_UART_SEL 107 139*4882a593Smuzhiyun #define CLK_TOP_SPI_SEL 108 140*4882a593Smuzhiyun #define CLK_TOP_USB20_SEL 109 141*4882a593Smuzhiyun #define CLK_TOP_USB30_SEL 110 142*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_HCLK_SEL 111 143*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_SEL 112 144*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1_SEL 113 145*4882a593Smuzhiyun #define CLK_TOP_MSDC30_2_SEL 114 146*4882a593Smuzhiyun #define CLK_TOP_MSDC30_3_SEL 115 147*4882a593Smuzhiyun #define CLK_TOP_AUDIO_SEL 116 148*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS_SEL 117 149*4882a593Smuzhiyun #define CLK_TOP_PMICSPI_SEL 118 150*4882a593Smuzhiyun #define CLK_TOP_DPILVDS1_SEL 119 151*4882a593Smuzhiyun #define CLK_TOP_ATB_SEL 120 152*4882a593Smuzhiyun #define CLK_TOP_NR_SEL 121 153*4882a593Smuzhiyun #define CLK_TOP_NFI2X_SEL 122 154*4882a593Smuzhiyun #define CLK_TOP_IRDA_SEL 123 155*4882a593Smuzhiyun #define CLK_TOP_CCI400_SEL 124 156*4882a593Smuzhiyun #define CLK_TOP_AUD_1_SEL 125 157*4882a593Smuzhiyun #define CLK_TOP_AUD_2_SEL 126 158*4882a593Smuzhiyun #define CLK_TOP_MEM_MFG_IN_AS_SEL 127 159*4882a593Smuzhiyun #define CLK_TOP_AXI_MFG_IN_AS_SEL 128 160*4882a593Smuzhiyun #define CLK_TOP_SCAM_SEL 129 161*4882a593Smuzhiyun #define CLK_TOP_NFIECC_SEL 130 162*4882a593Smuzhiyun #define CLK_TOP_PE2_MAC_P0_SEL 131 163*4882a593Smuzhiyun #define CLK_TOP_PE2_MAC_P1_SEL 132 164*4882a593Smuzhiyun #define CLK_TOP_DPILVDS_SEL 133 165*4882a593Smuzhiyun #define CLK_TOP_MSDC50_3_HCLK_SEL 134 166*4882a593Smuzhiyun #define CLK_TOP_HDCP_SEL 135 167*4882a593Smuzhiyun #define CLK_TOP_HDCP_24M_SEL 136 168*4882a593Smuzhiyun #define CLK_TOP_RTC_SEL 137 169*4882a593Smuzhiyun #define CLK_TOP_SPINOR_SEL 138 170*4882a593Smuzhiyun #define CLK_TOP_APLL_SEL 139 171*4882a593Smuzhiyun #define CLK_TOP_APLL2_SEL 140 172*4882a593Smuzhiyun #define CLK_TOP_A1SYS_HP_SEL 141 173*4882a593Smuzhiyun #define CLK_TOP_A2SYS_HP_SEL 142 174*4882a593Smuzhiyun #define CLK_TOP_ASM_L_SEL 143 175*4882a593Smuzhiyun #define CLK_TOP_ASM_M_SEL 144 176*4882a593Smuzhiyun #define CLK_TOP_ASM_H_SEL 145 177*4882a593Smuzhiyun #define CLK_TOP_I2SO1_SEL 146 178*4882a593Smuzhiyun #define CLK_TOP_I2SO2_SEL 147 179*4882a593Smuzhiyun #define CLK_TOP_I2SO3_SEL 148 180*4882a593Smuzhiyun #define CLK_TOP_TDMO0_SEL 149 181*4882a593Smuzhiyun #define CLK_TOP_TDMO1_SEL 150 182*4882a593Smuzhiyun #define CLK_TOP_I2SI1_SEL 151 183*4882a593Smuzhiyun #define CLK_TOP_I2SI2_SEL 152 184*4882a593Smuzhiyun #define CLK_TOP_I2SI3_SEL 153 185*4882a593Smuzhiyun #define CLK_TOP_ETHER_125M_SEL 154 186*4882a593Smuzhiyun #define CLK_TOP_ETHER_50M_SEL 155 187*4882a593Smuzhiyun #define CLK_TOP_JPGDEC_SEL 156 188*4882a593Smuzhiyun #define CLK_TOP_SPISLV_SEL 157 189*4882a593Smuzhiyun #define CLK_TOP_ETHER_50M_RMII_SEL 158 190*4882a593Smuzhiyun #define CLK_TOP_CAM2TG_SEL 159 191*4882a593Smuzhiyun #define CLK_TOP_DI_SEL 160 192*4882a593Smuzhiyun #define CLK_TOP_TVD_SEL 161 193*4882a593Smuzhiyun #define CLK_TOP_I2C_SEL 162 194*4882a593Smuzhiyun #define CLK_TOP_PWM_INFRA_SEL 163 195*4882a593Smuzhiyun #define CLK_TOP_MSDC0P_AES_SEL 164 196*4882a593Smuzhiyun #define CLK_TOP_CMSYS_SEL 165 197*4882a593Smuzhiyun #define CLK_TOP_GCPU_SEL 166 198*4882a593Smuzhiyun #define CLK_TOP_AUD_APLL1_SEL 167 199*4882a593Smuzhiyun #define CLK_TOP_AUD_APLL2_SEL 168 200*4882a593Smuzhiyun #define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169 201*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV0 170 202*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV1 171 203*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV2 172 204*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV3 173 205*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV4 174 206*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV5 175 207*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV6 176 208*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV7 177 209*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN0 178 210*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN1 179 211*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN2 180 212*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN3 181 213*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN4 182 214*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN5 183 215*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN6 184 216*4882a593Smuzhiyun #define CLK_TOP_APLL_DIV_PDN7 185 217*4882a593Smuzhiyun #define CLK_TOP_APLL1_D3 186 218*4882a593Smuzhiyun #define CLK_TOP_APLL1_REF_SEL 187 219*4882a593Smuzhiyun #define CLK_TOP_APLL2_REF_SEL 188 220*4882a593Smuzhiyun #define CLK_TOP_NFI2X_EN 189 221*4882a593Smuzhiyun #define CLK_TOP_NFIECC_EN 190 222*4882a593Smuzhiyun #define CLK_TOP_NFI1X_CK_EN 191 223*4882a593Smuzhiyun #define CLK_TOP_APLL2_D3 192 224*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 193 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun /* INFRACFG */ 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #define CLK_INFRA_DBGCLK 0 229*4882a593Smuzhiyun #define CLK_INFRA_GCE 1 230*4882a593Smuzhiyun #define CLK_INFRA_M4U 2 231*4882a593Smuzhiyun #define CLK_INFRA_KP 3 232*4882a593Smuzhiyun #define CLK_INFRA_AO_SPI0 4 233*4882a593Smuzhiyun #define CLK_INFRA_AO_SPI1 5 234*4882a593Smuzhiyun #define CLK_INFRA_AO_UART5 6 235*4882a593Smuzhiyun #define CLK_INFRA_NR_CLK 7 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* PERICFG */ 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #define CLK_PERI_NFI 0 240*4882a593Smuzhiyun #define CLK_PERI_THERM 1 241*4882a593Smuzhiyun #define CLK_PERI_PWM0 2 242*4882a593Smuzhiyun #define CLK_PERI_PWM1 3 243*4882a593Smuzhiyun #define CLK_PERI_PWM2 4 244*4882a593Smuzhiyun #define CLK_PERI_PWM3 5 245*4882a593Smuzhiyun #define CLK_PERI_PWM4 6 246*4882a593Smuzhiyun #define CLK_PERI_PWM5 7 247*4882a593Smuzhiyun #define CLK_PERI_PWM6 8 248*4882a593Smuzhiyun #define CLK_PERI_PWM7 9 249*4882a593Smuzhiyun #define CLK_PERI_PWM 10 250*4882a593Smuzhiyun #define CLK_PERI_AP_DMA 11 251*4882a593Smuzhiyun #define CLK_PERI_MSDC30_0 12 252*4882a593Smuzhiyun #define CLK_PERI_MSDC30_1 13 253*4882a593Smuzhiyun #define CLK_PERI_MSDC30_2 14 254*4882a593Smuzhiyun #define CLK_PERI_MSDC30_3 15 255*4882a593Smuzhiyun #define CLK_PERI_UART0 16 256*4882a593Smuzhiyun #define CLK_PERI_UART1 17 257*4882a593Smuzhiyun #define CLK_PERI_UART2 18 258*4882a593Smuzhiyun #define CLK_PERI_UART3 19 259*4882a593Smuzhiyun #define CLK_PERI_I2C0 20 260*4882a593Smuzhiyun #define CLK_PERI_I2C1 21 261*4882a593Smuzhiyun #define CLK_PERI_I2C2 22 262*4882a593Smuzhiyun #define CLK_PERI_I2C3 23 263*4882a593Smuzhiyun #define CLK_PERI_I2C4 24 264*4882a593Smuzhiyun #define CLK_PERI_AUXADC 25 265*4882a593Smuzhiyun #define CLK_PERI_SPI0 26 266*4882a593Smuzhiyun #define CLK_PERI_SPI 27 267*4882a593Smuzhiyun #define CLK_PERI_I2C5 28 268*4882a593Smuzhiyun #define CLK_PERI_SPI2 29 269*4882a593Smuzhiyun #define CLK_PERI_SPI3 30 270*4882a593Smuzhiyun #define CLK_PERI_SPI5 31 271*4882a593Smuzhiyun #define CLK_PERI_UART4 32 272*4882a593Smuzhiyun #define CLK_PERI_SFLASH 33 273*4882a593Smuzhiyun #define CLK_PERI_GMAC 34 274*4882a593Smuzhiyun #define CLK_PERI_PCIE0 35 275*4882a593Smuzhiyun #define CLK_PERI_PCIE1 36 276*4882a593Smuzhiyun #define CLK_PERI_GMAC_PCLK 37 277*4882a593Smuzhiyun #define CLK_PERI_MSDC50_0_EN 38 278*4882a593Smuzhiyun #define CLK_PERI_MSDC30_1_EN 39 279*4882a593Smuzhiyun #define CLK_PERI_MSDC30_2_EN 40 280*4882a593Smuzhiyun #define CLK_PERI_MSDC30_3_EN 41 281*4882a593Smuzhiyun #define CLK_PERI_MSDC50_0_HCLK_EN 42 282*4882a593Smuzhiyun #define CLK_PERI_MSDC50_3_HCLK_EN 43 283*4882a593Smuzhiyun #define CLK_PERI_MSDC30_0_QTR_EN 44 284*4882a593Smuzhiyun #define CLK_PERI_MSDC30_3_QTR_EN 45 285*4882a593Smuzhiyun #define CLK_PERI_NR_CLK 46 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* MCUCFG */ 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #define CLK_MCU_MP0_SEL 0 290*4882a593Smuzhiyun #define CLK_MCU_MP2_SEL 1 291*4882a593Smuzhiyun #define CLK_MCU_BUS_SEL 2 292*4882a593Smuzhiyun #define CLK_MCU_NR_CLK 3 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* MFGCFG */ 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun #define CLK_MFG_BG3D 0 297*4882a593Smuzhiyun #define CLK_MFG_NR_CLK 1 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* MMSYS */ 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 0 302*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 1 303*4882a593Smuzhiyun #define CLK_MM_CAM_MDP 2 304*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA0 3 305*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA1 4 306*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 5 307*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 6 308*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ2 7 309*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP0 8 310*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP1 9 311*4882a593Smuzhiyun #define CLK_MM_MDP_CROP 10 312*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA 11 313*4882a593Smuzhiyun #define CLK_MM_MDP_WROT0 12 314*4882a593Smuzhiyun #define CLK_MM_MDP_WROT1 13 315*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 14 316*4882a593Smuzhiyun #define CLK_MM_MUTEX_32K 15 317*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0 16 318*4882a593Smuzhiyun #define CLK_MM_DISP_OVL1 17 319*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA0 18 320*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA1 19 321*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA2 20 322*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA0 21 323*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA1 22 324*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR0 23 325*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR1 24 326*4882a593Smuzhiyun #define CLK_MM_DISP_AAL 25 327*4882a593Smuzhiyun #define CLK_MM_DISP_GAMMA 26 328*4882a593Smuzhiyun #define CLK_MM_DISP_UFOE 27 329*4882a593Smuzhiyun #define CLK_MM_DISP_SPLIT0 28 330*4882a593Smuzhiyun #define CLK_MM_DISP_OD 29 331*4882a593Smuzhiyun #define CLK_MM_DISP_PWM0_MM 30 332*4882a593Smuzhiyun #define CLK_MM_DISP_PWM0_26M 31 333*4882a593Smuzhiyun #define CLK_MM_DISP_PWM1_MM 32 334*4882a593Smuzhiyun #define CLK_MM_DISP_PWM1_26M 33 335*4882a593Smuzhiyun #define CLK_MM_DSI0_ENGINE 34 336*4882a593Smuzhiyun #define CLK_MM_DSI0_DIGITAL 35 337*4882a593Smuzhiyun #define CLK_MM_DSI1_ENGINE 36 338*4882a593Smuzhiyun #define CLK_MM_DSI1_DIGITAL 37 339*4882a593Smuzhiyun #define CLK_MM_DPI_PIXEL 38 340*4882a593Smuzhiyun #define CLK_MM_DPI_ENGINE 39 341*4882a593Smuzhiyun #define CLK_MM_DPI1_PIXEL 40 342*4882a593Smuzhiyun #define CLK_MM_DPI1_ENGINE 41 343*4882a593Smuzhiyun #define CLK_MM_LVDS_PIXEL 42 344*4882a593Smuzhiyun #define CLK_MM_LVDS_CTS 43 345*4882a593Smuzhiyun #define CLK_MM_SMI_LARB4 44 346*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON1 45 347*4882a593Smuzhiyun #define CLK_MM_SMI_LARB5 46 348*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA2 47 349*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP2 48 350*4882a593Smuzhiyun #define CLK_MM_DISP_OVL2 49 351*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA2 50 352*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR2 51 353*4882a593Smuzhiyun #define CLK_MM_DISP_AAL1 52 354*4882a593Smuzhiyun #define CLK_MM_DISP_OD1 53 355*4882a593Smuzhiyun #define CLK_MM_LVDS1_PIXEL 54 356*4882a593Smuzhiyun #define CLK_MM_LVDS1_CTS 55 357*4882a593Smuzhiyun #define CLK_MM_SMI_LARB7 56 358*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA3 57 359*4882a593Smuzhiyun #define CLK_MM_MDP_WROT2 58 360*4882a593Smuzhiyun #define CLK_MM_DSI2 59 361*4882a593Smuzhiyun #define CLK_MM_DSI2_DIGITAL 60 362*4882a593Smuzhiyun #define CLK_MM_DSI3 61 363*4882a593Smuzhiyun #define CLK_MM_DSI3_DIGITAL 62 364*4882a593Smuzhiyun #define CLK_MM_NR_CLK 63 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun /* IMGSYS */ 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun #define CLK_IMG_SMI_LARB2 0 369*4882a593Smuzhiyun #define CLK_IMG_SENINF_SCAM_EN 1 370*4882a593Smuzhiyun #define CLK_IMG_SENINF_CAM_EN 2 371*4882a593Smuzhiyun #define CLK_IMG_CAM_SV_EN 3 372*4882a593Smuzhiyun #define CLK_IMG_CAM_SV1_EN 4 373*4882a593Smuzhiyun #define CLK_IMG_CAM_SV2_EN 5 374*4882a593Smuzhiyun #define CLK_IMG_NR_CLK 6 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /* BDPSYS */ 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun #define CLK_BDP_BRIDGE_B 0 379*4882a593Smuzhiyun #define CLK_BDP_BRIDGE_DRAM 1 380*4882a593Smuzhiyun #define CLK_BDP_LARB_DRAM 2 381*4882a593Smuzhiyun #define CLK_BDP_WR_CHANNEL_VDI_PXL 3 382*4882a593Smuzhiyun #define CLK_BDP_WR_CHANNEL_VDI_DRAM 4 383*4882a593Smuzhiyun #define CLK_BDP_WR_CHANNEL_VDI_B 5 384*4882a593Smuzhiyun #define CLK_BDP_MT_B 6 385*4882a593Smuzhiyun #define CLK_BDP_DISPFMT_27M 7 386*4882a593Smuzhiyun #define CLK_BDP_DISPFMT_27M_VDOUT 8 387*4882a593Smuzhiyun #define CLK_BDP_DISPFMT_27_74_74 9 388*4882a593Smuzhiyun #define CLK_BDP_DISPFMT_2FS 10 389*4882a593Smuzhiyun #define CLK_BDP_DISPFMT_2FS_2FS74_148 11 390*4882a593Smuzhiyun #define CLK_BDP_DISPFMT_B 12 391*4882a593Smuzhiyun #define CLK_BDP_VDO_DRAM 13 392*4882a593Smuzhiyun #define CLK_BDP_VDO_2FS 14 393*4882a593Smuzhiyun #define CLK_BDP_VDO_B 15 394*4882a593Smuzhiyun #define CLK_BDP_WR_CHANNEL_DI_PXL 16 395*4882a593Smuzhiyun #define CLK_BDP_WR_CHANNEL_DI_DRAM 17 396*4882a593Smuzhiyun #define CLK_BDP_WR_CHANNEL_DI_B 18 397*4882a593Smuzhiyun #define CLK_BDP_NR_AGENT 19 398*4882a593Smuzhiyun #define CLK_BDP_NR_DRAM 20 399*4882a593Smuzhiyun #define CLK_BDP_NR_B 21 400*4882a593Smuzhiyun #define CLK_BDP_BRIDGE_RT_B 22 401*4882a593Smuzhiyun #define CLK_BDP_BRIDGE_RT_DRAM 23 402*4882a593Smuzhiyun #define CLK_BDP_LARB_RT_DRAM 24 403*4882a593Smuzhiyun #define CLK_BDP_TVD_TDC 25 404*4882a593Smuzhiyun #define CLK_BDP_TVD_54 26 405*4882a593Smuzhiyun #define CLK_BDP_TVD_CBUS 27 406*4882a593Smuzhiyun #define CLK_BDP_NR_CLK 28 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /* VDECSYS */ 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun #define CLK_VDEC_CKEN 0 411*4882a593Smuzhiyun #define CLK_VDEC_LARB1_CKEN 1 412*4882a593Smuzhiyun #define CLK_VDEC_IMGRZ_CKEN 2 413*4882a593Smuzhiyun #define CLK_VDEC_NR_CLK 3 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun /* VENCSYS */ 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun #define CLK_VENC_SMI_COMMON_CON 0 418*4882a593Smuzhiyun #define CLK_VENC_VENC 1 419*4882a593Smuzhiyun #define CLK_VENC_SMI_LARB6 2 420*4882a593Smuzhiyun #define CLK_VENC_NR_CLK 3 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun /* JPGDECSYS */ 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun #define CLK_JPGDEC_JPGDEC1 0 425*4882a593Smuzhiyun #define CLK_JPGDEC_JPGDEC 1 426*4882a593Smuzhiyun #define CLK_JPGDEC_NR_CLK 2 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT2712_H */ 429