1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Chen Zhong <chen.zhong@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT7622_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT7622_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* TOPCKGEN */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_TOP_TO_U2_PHY 0 13*4882a593Smuzhiyun #define CLK_TOP_TO_U2_PHY_1P 1 14*4882a593Smuzhiyun #define CLK_TOP_PCIE0_PIPE_EN 2 15*4882a593Smuzhiyun #define CLK_TOP_PCIE1_PIPE_EN 3 16*4882a593Smuzhiyun #define CLK_TOP_SSUSB_TX250M 4 17*4882a593Smuzhiyun #define CLK_TOP_SSUSB_EQ_RX250M 5 18*4882a593Smuzhiyun #define CLK_TOP_SSUSB_CDR_REF 6 19*4882a593Smuzhiyun #define CLK_TOP_SSUSB_CDR_FB 7 20*4882a593Smuzhiyun #define CLK_TOP_SATA_ASIC 8 21*4882a593Smuzhiyun #define CLK_TOP_SATA_RBC 9 22*4882a593Smuzhiyun #define CLK_TOP_TO_USB3_SYS 10 23*4882a593Smuzhiyun #define CLK_TOP_P1_1MHZ 11 24*4882a593Smuzhiyun #define CLK_TOP_4MHZ 12 25*4882a593Smuzhiyun #define CLK_TOP_P0_1MHZ 13 26*4882a593Smuzhiyun #define CLK_TOP_TXCLK_SRC_PRE 14 27*4882a593Smuzhiyun #define CLK_TOP_RTC 15 28*4882a593Smuzhiyun #define CLK_TOP_MEMPLL 16 29*4882a593Smuzhiyun #define CLK_TOP_DMPLL 17 30*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 18 31*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D2 19 32*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D4 20 33*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D8 21 34*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D4 22 35*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D8 23 36*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 24 37*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D2 25 38*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D4 26 39*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D2 27 40*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D4 28 41*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D16 29 42*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL 30 43*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 31 44*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 32 45*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 33 46*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D8 34 47*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D16 35 48*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 36 49*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 37 50*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 38 51*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D16 39 52*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 40 53*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D2 41 54*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D4 42 55*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D16 43 56*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 44 57*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D80_D4 45 58*4882a593Smuzhiyun #define CLK_TOP_UNIV48M 46 59*4882a593Smuzhiyun #define CLK_TOP_SGMIIPLL 47 60*4882a593Smuzhiyun #define CLK_TOP_SGMIIPLL_D2 48 61*4882a593Smuzhiyun #define CLK_TOP_AUD1PLL 49 62*4882a593Smuzhiyun #define CLK_TOP_AUD2PLL 50 63*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S2_MCK 51 64*4882a593Smuzhiyun #define CLK_TOP_TO_USB3_REF 52 65*4882a593Smuzhiyun #define CLK_TOP_PCIE1_MAC_EN 53 66*4882a593Smuzhiyun #define CLK_TOP_PCIE0_MAC_EN 54 67*4882a593Smuzhiyun #define CLK_TOP_ETH_500M 55 68*4882a593Smuzhiyun #define CLK_TOP_AXI_SEL 56 69*4882a593Smuzhiyun #define CLK_TOP_MEM_SEL 57 70*4882a593Smuzhiyun #define CLK_TOP_DDRPHYCFG_SEL 58 71*4882a593Smuzhiyun #define CLK_TOP_ETH_SEL 59 72*4882a593Smuzhiyun #define CLK_TOP_PWM_SEL 60 73*4882a593Smuzhiyun #define CLK_TOP_F10M_REF_SEL 61 74*4882a593Smuzhiyun #define CLK_TOP_NFI_INFRA_SEL 62 75*4882a593Smuzhiyun #define CLK_TOP_FLASH_SEL 63 76*4882a593Smuzhiyun #define CLK_TOP_UART_SEL 64 77*4882a593Smuzhiyun #define CLK_TOP_SPI0_SEL 65 78*4882a593Smuzhiyun #define CLK_TOP_SPI1_SEL 66 79*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_SEL 67 80*4882a593Smuzhiyun #define CLK_TOP_MSDC30_0_SEL 68 81*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1_SEL 69 82*4882a593Smuzhiyun #define CLK_TOP_A1SYS_HP_SEL 70 83*4882a593Smuzhiyun #define CLK_TOP_A2SYS_HP_SEL 71 84*4882a593Smuzhiyun #define CLK_TOP_INTDIR_SEL 72 85*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS_SEL 73 86*4882a593Smuzhiyun #define CLK_TOP_PMICSPI_SEL 74 87*4882a593Smuzhiyun #define CLK_TOP_SCP_SEL 75 88*4882a593Smuzhiyun #define CLK_TOP_ATB_SEL 76 89*4882a593Smuzhiyun #define CLK_TOP_HIF_SEL 77 90*4882a593Smuzhiyun #define CLK_TOP_AUDIO_SEL 78 91*4882a593Smuzhiyun #define CLK_TOP_U2_SEL 79 92*4882a593Smuzhiyun #define CLK_TOP_AUD1_SEL 80 93*4882a593Smuzhiyun #define CLK_TOP_AUD2_SEL 81 94*4882a593Smuzhiyun #define CLK_TOP_IRRX_SEL 82 95*4882a593Smuzhiyun #define CLK_TOP_IRTX_SEL 83 96*4882a593Smuzhiyun #define CLK_TOP_ASM_L_SEL 84 97*4882a593Smuzhiyun #define CLK_TOP_ASM_M_SEL 85 98*4882a593Smuzhiyun #define CLK_TOP_ASM_H_SEL 86 99*4882a593Smuzhiyun #define CLK_TOP_APLL1_SEL 87 100*4882a593Smuzhiyun #define CLK_TOP_APLL2_SEL 88 101*4882a593Smuzhiyun #define CLK_TOP_I2S0_MCK_SEL 89 102*4882a593Smuzhiyun #define CLK_TOP_I2S1_MCK_SEL 90 103*4882a593Smuzhiyun #define CLK_TOP_I2S2_MCK_SEL 91 104*4882a593Smuzhiyun #define CLK_TOP_I2S3_MCK_SEL 92 105*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV 93 106*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV 94 107*4882a593Smuzhiyun #define CLK_TOP_I2S0_MCK_DIV 95 108*4882a593Smuzhiyun #define CLK_TOP_I2S1_MCK_DIV 96 109*4882a593Smuzhiyun #define CLK_TOP_I2S2_MCK_DIV 97 110*4882a593Smuzhiyun #define CLK_TOP_I2S3_MCK_DIV 98 111*4882a593Smuzhiyun #define CLK_TOP_A1SYS_HP_DIV 99 112*4882a593Smuzhiyun #define CLK_TOP_A2SYS_HP_DIV 100 113*4882a593Smuzhiyun #define CLK_TOP_APLL1_DIV_PD 101 114*4882a593Smuzhiyun #define CLK_TOP_APLL2_DIV_PD 102 115*4882a593Smuzhiyun #define CLK_TOP_I2S0_MCK_DIV_PD 103 116*4882a593Smuzhiyun #define CLK_TOP_I2S1_MCK_DIV_PD 104 117*4882a593Smuzhiyun #define CLK_TOP_I2S2_MCK_DIV_PD 105 118*4882a593Smuzhiyun #define CLK_TOP_I2S3_MCK_DIV_PD 106 119*4882a593Smuzhiyun #define CLK_TOP_A1SYS_HP_DIV_PD 107 120*4882a593Smuzhiyun #define CLK_TOP_A2SYS_HP_DIV_PD 108 121*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 109 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* INFRACFG */ 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define CLK_INFRA_MUX1_SEL 0 126*4882a593Smuzhiyun #define CLK_INFRA_DBGCLK_PD 1 127*4882a593Smuzhiyun #define CLK_INFRA_AUDIO_PD 2 128*4882a593Smuzhiyun #define CLK_INFRA_IRRX_PD 3 129*4882a593Smuzhiyun #define CLK_INFRA_APXGPT_PD 4 130*4882a593Smuzhiyun #define CLK_INFRA_PMIC_PD 5 131*4882a593Smuzhiyun #define CLK_INFRA_TRNG 6 132*4882a593Smuzhiyun #define CLK_INFRA_NR_CLK 7 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* PERICFG */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define CLK_PERIBUS_SEL 0 137*4882a593Smuzhiyun #define CLK_PERI_THERM_PD 1 138*4882a593Smuzhiyun #define CLK_PERI_PWM1_PD 2 139*4882a593Smuzhiyun #define CLK_PERI_PWM2_PD 3 140*4882a593Smuzhiyun #define CLK_PERI_PWM3_PD 4 141*4882a593Smuzhiyun #define CLK_PERI_PWM4_PD 5 142*4882a593Smuzhiyun #define CLK_PERI_PWM5_PD 6 143*4882a593Smuzhiyun #define CLK_PERI_PWM6_PD 7 144*4882a593Smuzhiyun #define CLK_PERI_PWM7_PD 8 145*4882a593Smuzhiyun #define CLK_PERI_PWM_PD 9 146*4882a593Smuzhiyun #define CLK_PERI_AP_DMA_PD 10 147*4882a593Smuzhiyun #define CLK_PERI_MSDC30_0_PD 11 148*4882a593Smuzhiyun #define CLK_PERI_MSDC30_1_PD 12 149*4882a593Smuzhiyun #define CLK_PERI_UART0_PD 13 150*4882a593Smuzhiyun #define CLK_PERI_UART1_PD 14 151*4882a593Smuzhiyun #define CLK_PERI_UART2_PD 15 152*4882a593Smuzhiyun #define CLK_PERI_UART3_PD 16 153*4882a593Smuzhiyun #define CLK_PERI_UART4_PD 17 154*4882a593Smuzhiyun #define CLK_PERI_BTIF_PD 18 155*4882a593Smuzhiyun #define CLK_PERI_I2C0_PD 19 156*4882a593Smuzhiyun #define CLK_PERI_I2C1_PD 20 157*4882a593Smuzhiyun #define CLK_PERI_I2C2_PD 21 158*4882a593Smuzhiyun #define CLK_PERI_SPI1_PD 22 159*4882a593Smuzhiyun #define CLK_PERI_AUXADC_PD 23 160*4882a593Smuzhiyun #define CLK_PERI_SPI0_PD 24 161*4882a593Smuzhiyun #define CLK_PERI_SNFI_PD 25 162*4882a593Smuzhiyun #define CLK_PERI_NFI_PD 26 163*4882a593Smuzhiyun #define CLK_PERI_NFIECC_PD 27 164*4882a593Smuzhiyun #define CLK_PERI_FLASH_PD 28 165*4882a593Smuzhiyun #define CLK_PERI_IRTX_PD 29 166*4882a593Smuzhiyun #define CLK_PERI_NR_CLK 30 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* APMIXEDSYS */ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL 0 171*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 1 172*4882a593Smuzhiyun #define CLK_APMIXED_UNIV2PLL 2 173*4882a593Smuzhiyun #define CLK_APMIXED_ETH1PLL 3 174*4882a593Smuzhiyun #define CLK_APMIXED_ETH2PLL 4 175*4882a593Smuzhiyun #define CLK_APMIXED_AUD1PLL 5 176*4882a593Smuzhiyun #define CLK_APMIXED_AUD2PLL 6 177*4882a593Smuzhiyun #define CLK_APMIXED_TRGPLL 7 178*4882a593Smuzhiyun #define CLK_APMIXED_SGMIPLL 8 179*4882a593Smuzhiyun #define CLK_APMIXED_MAIN_CORE_EN 9 180*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 10 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* AUDIOSYS */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define CLK_AUDIO_AFE 0 185*4882a593Smuzhiyun #define CLK_AUDIO_HDMI 1 186*4882a593Smuzhiyun #define CLK_AUDIO_SPDF 2 187*4882a593Smuzhiyun #define CLK_AUDIO_APLL 3 188*4882a593Smuzhiyun #define CLK_AUDIO_I2SIN1 4 189*4882a593Smuzhiyun #define CLK_AUDIO_I2SIN2 5 190*4882a593Smuzhiyun #define CLK_AUDIO_I2SIN3 6 191*4882a593Smuzhiyun #define CLK_AUDIO_I2SIN4 7 192*4882a593Smuzhiyun #define CLK_AUDIO_I2SO1 8 193*4882a593Smuzhiyun #define CLK_AUDIO_I2SO2 9 194*4882a593Smuzhiyun #define CLK_AUDIO_I2SO3 10 195*4882a593Smuzhiyun #define CLK_AUDIO_I2SO4 11 196*4882a593Smuzhiyun #define CLK_AUDIO_ASRCI1 12 197*4882a593Smuzhiyun #define CLK_AUDIO_ASRCI2 13 198*4882a593Smuzhiyun #define CLK_AUDIO_ASRCO1 14 199*4882a593Smuzhiyun #define CLK_AUDIO_ASRCO2 15 200*4882a593Smuzhiyun #define CLK_AUDIO_INTDIR 16 201*4882a593Smuzhiyun #define CLK_AUDIO_A1SYS 17 202*4882a593Smuzhiyun #define CLK_AUDIO_A2SYS 18 203*4882a593Smuzhiyun #define CLK_AUDIO_UL1 19 204*4882a593Smuzhiyun #define CLK_AUDIO_UL2 20 205*4882a593Smuzhiyun #define CLK_AUDIO_UL3 21 206*4882a593Smuzhiyun #define CLK_AUDIO_UL4 22 207*4882a593Smuzhiyun #define CLK_AUDIO_UL5 23 208*4882a593Smuzhiyun #define CLK_AUDIO_UL6 24 209*4882a593Smuzhiyun #define CLK_AUDIO_DL1 25 210*4882a593Smuzhiyun #define CLK_AUDIO_DL2 26 211*4882a593Smuzhiyun #define CLK_AUDIO_DL3 27 212*4882a593Smuzhiyun #define CLK_AUDIO_DL4 28 213*4882a593Smuzhiyun #define CLK_AUDIO_DL5 29 214*4882a593Smuzhiyun #define CLK_AUDIO_DL6 30 215*4882a593Smuzhiyun #define CLK_AUDIO_DLMCH 31 216*4882a593Smuzhiyun #define CLK_AUDIO_ARB1 32 217*4882a593Smuzhiyun #define CLK_AUDIO_AWB 33 218*4882a593Smuzhiyun #define CLK_AUDIO_AWB2 34 219*4882a593Smuzhiyun #define CLK_AUDIO_DAI 35 220*4882a593Smuzhiyun #define CLK_AUDIO_MOD 36 221*4882a593Smuzhiyun #define CLK_AUDIO_ASRCI3 37 222*4882a593Smuzhiyun #define CLK_AUDIO_ASRCI4 38 223*4882a593Smuzhiyun #define CLK_AUDIO_ASRCO3 39 224*4882a593Smuzhiyun #define CLK_AUDIO_ASRCO4 40 225*4882a593Smuzhiyun #define CLK_AUDIO_MEM_ASRC1 41 226*4882a593Smuzhiyun #define CLK_AUDIO_MEM_ASRC2 42 227*4882a593Smuzhiyun #define CLK_AUDIO_MEM_ASRC3 43 228*4882a593Smuzhiyun #define CLK_AUDIO_MEM_ASRC4 44 229*4882a593Smuzhiyun #define CLK_AUDIO_MEM_ASRC5 45 230*4882a593Smuzhiyun #define CLK_AUDIO_AFE_CONN 46 231*4882a593Smuzhiyun #define CLK_AUDIO_NR_CLK 47 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /* SSUSBSYS */ 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #define CLK_SSUSB_U2_PHY_1P_EN 0 236*4882a593Smuzhiyun #define CLK_SSUSB_U2_PHY_EN 1 237*4882a593Smuzhiyun #define CLK_SSUSB_REF_EN 2 238*4882a593Smuzhiyun #define CLK_SSUSB_SYS_EN 3 239*4882a593Smuzhiyun #define CLK_SSUSB_MCU_EN 4 240*4882a593Smuzhiyun #define CLK_SSUSB_DMA_EN 5 241*4882a593Smuzhiyun #define CLK_SSUSB_NR_CLK 6 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* PCIESYS */ 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define CLK_PCIE_P1_AUX_EN 0 246*4882a593Smuzhiyun #define CLK_PCIE_P1_OBFF_EN 1 247*4882a593Smuzhiyun #define CLK_PCIE_P1_AHB_EN 2 248*4882a593Smuzhiyun #define CLK_PCIE_P1_AXI_EN 3 249*4882a593Smuzhiyun #define CLK_PCIE_P1_MAC_EN 4 250*4882a593Smuzhiyun #define CLK_PCIE_P1_PIPE_EN 5 251*4882a593Smuzhiyun #define CLK_PCIE_P0_AUX_EN 6 252*4882a593Smuzhiyun #define CLK_PCIE_P0_OBFF_EN 7 253*4882a593Smuzhiyun #define CLK_PCIE_P0_AHB_EN 8 254*4882a593Smuzhiyun #define CLK_PCIE_P0_AXI_EN 9 255*4882a593Smuzhiyun #define CLK_PCIE_P0_MAC_EN 10 256*4882a593Smuzhiyun #define CLK_PCIE_P0_PIPE_EN 11 257*4882a593Smuzhiyun #define CLK_SATA_AHB_EN 12 258*4882a593Smuzhiyun #define CLK_SATA_AXI_EN 13 259*4882a593Smuzhiyun #define CLK_SATA_ASIC_EN 14 260*4882a593Smuzhiyun #define CLK_SATA_RBC_EN 15 261*4882a593Smuzhiyun #define CLK_SATA_PM_EN 16 262*4882a593Smuzhiyun #define CLK_PCIE_NR_CLK 17 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* ETHSYS */ 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #define CLK_ETH_HSDMA_EN 0 267*4882a593Smuzhiyun #define CLK_ETH_ESW_EN 1 268*4882a593Smuzhiyun #define CLK_ETH_GP2_EN 2 269*4882a593Smuzhiyun #define CLK_ETH_GP1_EN 3 270*4882a593Smuzhiyun #define CLK_ETH_GP0_EN 4 271*4882a593Smuzhiyun #define CLK_ETH_NR_CLK 5 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* SGMIISYS */ 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define CLK_SGMII_TX250M_EN 0 276*4882a593Smuzhiyun #define CLK_SGMII_RX250M_EN 1 277*4882a593Smuzhiyun #define CLK_SGMII_CDR_REF 2 278*4882a593Smuzhiyun #define CLK_SGMII_CDR_FB 3 279*4882a593Smuzhiyun #define CLK_SGMII_NR_CLK 4 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT7622_H */ 282*4882a593Smuzhiyun 283