1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Shunli Wang <shunli.wang@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT2701_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT2701_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* TOPCKGEN */ 11*4882a593Smuzhiyun #define CLK_TOP_SYSPLL 1 12*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 2 13*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3 3 14*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 4 15*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7 5 16*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D2 6 17*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D4 7 18*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D8 8 19*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D16 9 20*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D2 10 21*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D4 11 22*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D8 12 23*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D2 13 24*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D4 14 25*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D2 15 26*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D4 16 27*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL 17 28*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 18 29*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 19 30*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 20 31*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 21 32*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D26 22 33*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D52 23 34*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D108 24 35*4882a593Smuzhiyun #define CLK_TOP_USB_PHY48M 25 36*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 26 37*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 27 38*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D8 28 39*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 29 40*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 30 41*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 31 42*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D16 32 43*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D32 33 44*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D2 34 45*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D4 35 46*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D8 36 47*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL 37 48*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D2 38 49*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D4 39 50*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D8 40 51*4882a593Smuzhiyun #define CLK_TOP_MMPLL 41 52*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D2 42 53*4882a593Smuzhiyun #define CLK_TOP_DMPLL 43 54*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D2 44 55*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D4 45 56*4882a593Smuzhiyun #define CLK_TOP_DMPLL_X2 46 57*4882a593Smuzhiyun #define CLK_TOP_TVDPLL 47 58*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D2 48 59*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D4 49 60*4882a593Smuzhiyun #define CLK_TOP_TVD2PLL 50 61*4882a593Smuzhiyun #define CLK_TOP_TVD2PLL_D2 51 62*4882a593Smuzhiyun #define CLK_TOP_HADDS2PLL_98M 52 63*4882a593Smuzhiyun #define CLK_TOP_HADDS2PLL_294M 53 64*4882a593Smuzhiyun #define CLK_TOP_HADDS2_FB 54 65*4882a593Smuzhiyun #define CLK_TOP_MIPIPLL_D2 55 66*4882a593Smuzhiyun #define CLK_TOP_MIPIPLL_D4 56 67*4882a593Smuzhiyun #define CLK_TOP_HDMIPLL 57 68*4882a593Smuzhiyun #define CLK_TOP_HDMIPLL_D2 58 69*4882a593Smuzhiyun #define CLK_TOP_HDMIPLL_D3 59 70*4882a593Smuzhiyun #define CLK_TOP_HDMI_SCL_RX 60 71*4882a593Smuzhiyun #define CLK_TOP_HDMI_0_PIX340M 61 72*4882a593Smuzhiyun #define CLK_TOP_HDMI_0_DEEP340M 62 73*4882a593Smuzhiyun #define CLK_TOP_HDMI_0_PLL340M 63 74*4882a593Smuzhiyun #define CLK_TOP_AUD1PLL_98M 64 75*4882a593Smuzhiyun #define CLK_TOP_AUD2PLL_90M 65 76*4882a593Smuzhiyun #define CLK_TOP_AUDPLL 66 77*4882a593Smuzhiyun #define CLK_TOP_AUDPLL_D4 67 78*4882a593Smuzhiyun #define CLK_TOP_AUDPLL_D8 68 79*4882a593Smuzhiyun #define CLK_TOP_AUDPLL_D16 69 80*4882a593Smuzhiyun #define CLK_TOP_AUDPLL_D24 70 81*4882a593Smuzhiyun #define CLK_TOP_ETHPLL_500M 71 82*4882a593Smuzhiyun #define CLK_TOP_VDECPLL 72 83*4882a593Smuzhiyun #define CLK_TOP_VENCPLL 73 84*4882a593Smuzhiyun #define CLK_TOP_MIPIPLL 74 85*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_1P3G 75 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define CLK_TOP_MM_SEL 76 88*4882a593Smuzhiyun #define CLK_TOP_DDRPHYCFG_SEL 77 89*4882a593Smuzhiyun #define CLK_TOP_MEM_SEL 78 90*4882a593Smuzhiyun #define CLK_TOP_AXI_SEL 79 91*4882a593Smuzhiyun #define CLK_TOP_CAMTG_SEL 80 92*4882a593Smuzhiyun #define CLK_TOP_MFG_SEL 81 93*4882a593Smuzhiyun #define CLK_TOP_VDEC_SEL 82 94*4882a593Smuzhiyun #define CLK_TOP_PWM_SEL 83 95*4882a593Smuzhiyun #define CLK_TOP_MSDC30_0_SEL 84 96*4882a593Smuzhiyun #define CLK_TOP_USB20_SEL 85 97*4882a593Smuzhiyun #define CLK_TOP_SPI0_SEL 86 98*4882a593Smuzhiyun #define CLK_TOP_UART_SEL 87 99*4882a593Smuzhiyun #define CLK_TOP_AUDINTBUS_SEL 88 100*4882a593Smuzhiyun #define CLK_TOP_AUDIO_SEL 89 101*4882a593Smuzhiyun #define CLK_TOP_MSDC30_2_SEL 90 102*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1_SEL 91 103*4882a593Smuzhiyun #define CLK_TOP_DPI1_SEL 92 104*4882a593Smuzhiyun #define CLK_TOP_DPI0_SEL 93 105*4882a593Smuzhiyun #define CLK_TOP_SCP_SEL 94 106*4882a593Smuzhiyun #define CLK_TOP_PMICSPI_SEL 95 107*4882a593Smuzhiyun #define CLK_TOP_APLL_SEL 96 108*4882a593Smuzhiyun #define CLK_TOP_HDMI_SEL 97 109*4882a593Smuzhiyun #define CLK_TOP_TVE_SEL 98 110*4882a593Smuzhiyun #define CLK_TOP_EMMC_HCLK_SEL 99 111*4882a593Smuzhiyun #define CLK_TOP_NFI2X_SEL 100 112*4882a593Smuzhiyun #define CLK_TOP_RTC_SEL 101 113*4882a593Smuzhiyun #define CLK_TOP_OSD_SEL 102 114*4882a593Smuzhiyun #define CLK_TOP_NR_SEL 103 115*4882a593Smuzhiyun #define CLK_TOP_DI_SEL 104 116*4882a593Smuzhiyun #define CLK_TOP_FLASH_SEL 105 117*4882a593Smuzhiyun #define CLK_TOP_ASM_M_SEL 106 118*4882a593Smuzhiyun #define CLK_TOP_ASM_I_SEL 107 119*4882a593Smuzhiyun #define CLK_TOP_INTDIR_SEL 108 120*4882a593Smuzhiyun #define CLK_TOP_HDMIRX_BIST_SEL 109 121*4882a593Smuzhiyun #define CLK_TOP_ETHIF_SEL 110 122*4882a593Smuzhiyun #define CLK_TOP_MS_CARD_SEL 111 123*4882a593Smuzhiyun #define CLK_TOP_ASM_H_SEL 112 124*4882a593Smuzhiyun #define CLK_TOP_SPI1_SEL 113 125*4882a593Smuzhiyun #define CLK_TOP_CMSYS_SEL 114 126*4882a593Smuzhiyun #define CLK_TOP_MSDC30_3_SEL 115 127*4882a593Smuzhiyun #define CLK_TOP_HDMIRX26_24_SEL 116 128*4882a593Smuzhiyun #define CLK_TOP_AUD2DVD_SEL 117 129*4882a593Smuzhiyun #define CLK_TOP_8BDAC_SEL 118 130*4882a593Smuzhiyun #define CLK_TOP_SPI2_SEL 119 131*4882a593Smuzhiyun #define CLK_TOP_AUD_MUX1_SEL 120 132*4882a593Smuzhiyun #define CLK_TOP_AUD_MUX2_SEL 121 133*4882a593Smuzhiyun #define CLK_TOP_AUDPLL_MUX_SEL 122 134*4882a593Smuzhiyun #define CLK_TOP_AUD_K1_SRC_SEL 123 135*4882a593Smuzhiyun #define CLK_TOP_AUD_K2_SRC_SEL 124 136*4882a593Smuzhiyun #define CLK_TOP_AUD_K3_SRC_SEL 125 137*4882a593Smuzhiyun #define CLK_TOP_AUD_K4_SRC_SEL 126 138*4882a593Smuzhiyun #define CLK_TOP_AUD_K5_SRC_SEL 127 139*4882a593Smuzhiyun #define CLK_TOP_AUD_K6_SRC_SEL 128 140*4882a593Smuzhiyun #define CLK_TOP_PADMCLK_SEL 129 141*4882a593Smuzhiyun #define CLK_TOP_AUD_EXTCK1_DIV 130 142*4882a593Smuzhiyun #define CLK_TOP_AUD_EXTCK2_DIV 131 143*4882a593Smuzhiyun #define CLK_TOP_AUD_MUX1_DIV 132 144*4882a593Smuzhiyun #define CLK_TOP_AUD_MUX2_DIV 133 145*4882a593Smuzhiyun #define CLK_TOP_AUD_K1_SRC_DIV 134 146*4882a593Smuzhiyun #define CLK_TOP_AUD_K2_SRC_DIV 135 147*4882a593Smuzhiyun #define CLK_TOP_AUD_K3_SRC_DIV 136 148*4882a593Smuzhiyun #define CLK_TOP_AUD_K4_SRC_DIV 137 149*4882a593Smuzhiyun #define CLK_TOP_AUD_K5_SRC_DIV 138 150*4882a593Smuzhiyun #define CLK_TOP_AUD_K6_SRC_DIV 139 151*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S1_MCLK 140 152*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S2_MCLK 141 153*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S3_MCLK 142 154*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S4_MCLK 143 155*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S5_MCLK 144 156*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S6_MCLK 145 157*4882a593Smuzhiyun #define CLK_TOP_AUD_48K_TIMING 146 158*4882a593Smuzhiyun #define CLK_TOP_AUD_44K_TIMING 147 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define CLK_TOP_32K_INTERNAL 148 161*4882a593Smuzhiyun #define CLK_TOP_32K_EXTERNAL 149 162*4882a593Smuzhiyun #define CLK_TOP_CLK26M_D8 150 163*4882a593Smuzhiyun #define CLK_TOP_8BDAC 151 164*4882a593Smuzhiyun #define CLK_TOP_WBG_DIG_416M 152 165*4882a593Smuzhiyun #define CLK_TOP_DPI 153 166*4882a593Smuzhiyun #define CLK_TOP_DSI0_LNTC_DSI 154 167*4882a593Smuzhiyun #define CLK_TOP_AUD_EXT1 155 168*4882a593Smuzhiyun #define CLK_TOP_AUD_EXT2 156 169*4882a593Smuzhiyun #define CLK_TOP_NFI1X_PAD 157 170*4882a593Smuzhiyun #define CLK_TOP_AXISEL_D4 158 171*4882a593Smuzhiyun #define CLK_TOP_NR 159 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun /* APMIXEDSYS */ 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL 1 176*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 2 177*4882a593Smuzhiyun #define CLK_APMIXED_UNIVPLL 3 178*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 4 179*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 5 180*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL 6 181*4882a593Smuzhiyun #define CLK_APMIXED_AUD1PLL 7 182*4882a593Smuzhiyun #define CLK_APMIXED_TRGPLL 8 183*4882a593Smuzhiyun #define CLK_APMIXED_ETHPLL 9 184*4882a593Smuzhiyun #define CLK_APMIXED_VDECPLL 10 185*4882a593Smuzhiyun #define CLK_APMIXED_HADDS2PLL 11 186*4882a593Smuzhiyun #define CLK_APMIXED_AUD2PLL 12 187*4882a593Smuzhiyun #define CLK_APMIXED_TVD2PLL 13 188*4882a593Smuzhiyun #define CLK_APMIXED_HDMI_REF 14 189*4882a593Smuzhiyun #define CLK_APMIXED_NR 15 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* DDRPHY */ 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define CLK_DDRPHY_VENCPLL 1 194*4882a593Smuzhiyun #define CLK_DDRPHY_NR 2 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* INFRACFG */ 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun #define CLK_INFRA_DBG 1 199*4882a593Smuzhiyun #define CLK_INFRA_SMI 2 200*4882a593Smuzhiyun #define CLK_INFRA_QAXI_CM4 3 201*4882a593Smuzhiyun #define CLK_INFRA_AUD_SPLIN_B 4 202*4882a593Smuzhiyun #define CLK_INFRA_AUDIO 5 203*4882a593Smuzhiyun #define CLK_INFRA_EFUSE 6 204*4882a593Smuzhiyun #define CLK_INFRA_L2C_SRAM 7 205*4882a593Smuzhiyun #define CLK_INFRA_M4U 8 206*4882a593Smuzhiyun #define CLK_INFRA_CONNMCU 9 207*4882a593Smuzhiyun #define CLK_INFRA_TRNG 10 208*4882a593Smuzhiyun #define CLK_INFRA_RAMBUFIF 11 209*4882a593Smuzhiyun #define CLK_INFRA_CPUM 12 210*4882a593Smuzhiyun #define CLK_INFRA_KP 13 211*4882a593Smuzhiyun #define CLK_INFRA_CEC 14 212*4882a593Smuzhiyun #define CLK_INFRA_IRRX 15 213*4882a593Smuzhiyun #define CLK_INFRA_PMICSPI 16 214*4882a593Smuzhiyun #define CLK_INFRA_PMICWRAP 17 215*4882a593Smuzhiyun #define CLK_INFRA_DDCCI 18 216*4882a593Smuzhiyun #define CLK_INFRA_CLK_13M 19 217*4882a593Smuzhiyun #define CLK_INFRA_CPUSEL 20 218*4882a593Smuzhiyun #define CLK_INFRA_NR 21 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* PERICFG */ 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #define CLK_PERI_NFI 1 223*4882a593Smuzhiyun #define CLK_PERI_THERM 2 224*4882a593Smuzhiyun #define CLK_PERI_PWM1 3 225*4882a593Smuzhiyun #define CLK_PERI_PWM2 4 226*4882a593Smuzhiyun #define CLK_PERI_PWM3 5 227*4882a593Smuzhiyun #define CLK_PERI_PWM4 6 228*4882a593Smuzhiyun #define CLK_PERI_PWM5 7 229*4882a593Smuzhiyun #define CLK_PERI_PWM6 8 230*4882a593Smuzhiyun #define CLK_PERI_PWM7 9 231*4882a593Smuzhiyun #define CLK_PERI_PWM 10 232*4882a593Smuzhiyun #define CLK_PERI_USB0 11 233*4882a593Smuzhiyun #define CLK_PERI_USB1 12 234*4882a593Smuzhiyun #define CLK_PERI_AP_DMA 13 235*4882a593Smuzhiyun #define CLK_PERI_MSDC30_0 14 236*4882a593Smuzhiyun #define CLK_PERI_MSDC30_1 15 237*4882a593Smuzhiyun #define CLK_PERI_MSDC30_2 16 238*4882a593Smuzhiyun #define CLK_PERI_MSDC30_3 17 239*4882a593Smuzhiyun #define CLK_PERI_MSDC50_3 18 240*4882a593Smuzhiyun #define CLK_PERI_NLI 19 241*4882a593Smuzhiyun #define CLK_PERI_UART0 20 242*4882a593Smuzhiyun #define CLK_PERI_UART1 21 243*4882a593Smuzhiyun #define CLK_PERI_UART2 22 244*4882a593Smuzhiyun #define CLK_PERI_UART3 23 245*4882a593Smuzhiyun #define CLK_PERI_BTIF 24 246*4882a593Smuzhiyun #define CLK_PERI_I2C0 25 247*4882a593Smuzhiyun #define CLK_PERI_I2C1 26 248*4882a593Smuzhiyun #define CLK_PERI_I2C2 27 249*4882a593Smuzhiyun #define CLK_PERI_I2C3 28 250*4882a593Smuzhiyun #define CLK_PERI_AUXADC 29 251*4882a593Smuzhiyun #define CLK_PERI_SPI0 30 252*4882a593Smuzhiyun #define CLK_PERI_ETH 31 253*4882a593Smuzhiyun #define CLK_PERI_USB0_MCU 32 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun #define CLK_PERI_USB1_MCU 33 256*4882a593Smuzhiyun #define CLK_PERI_USB_SLV 34 257*4882a593Smuzhiyun #define CLK_PERI_GCPU 35 258*4882a593Smuzhiyun #define CLK_PERI_NFI_ECC 36 259*4882a593Smuzhiyun #define CLK_PERI_NFI_PAD 37 260*4882a593Smuzhiyun #define CLK_PERI_FLASH 38 261*4882a593Smuzhiyun #define CLK_PERI_HOST89_INT 39 262*4882a593Smuzhiyun #define CLK_PERI_HOST89_SPI 40 263*4882a593Smuzhiyun #define CLK_PERI_HOST89_DVD 41 264*4882a593Smuzhiyun #define CLK_PERI_SPI1 42 265*4882a593Smuzhiyun #define CLK_PERI_SPI2 43 266*4882a593Smuzhiyun #define CLK_PERI_FCI 44 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #define CLK_PERI_UART0_SEL 45 269*4882a593Smuzhiyun #define CLK_PERI_UART1_SEL 46 270*4882a593Smuzhiyun #define CLK_PERI_UART2_SEL 47 271*4882a593Smuzhiyun #define CLK_PERI_UART3_SEL 48 272*4882a593Smuzhiyun #define CLK_PERI_NR 49 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* AUDIO */ 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define CLK_AUD_AFE 1 277*4882a593Smuzhiyun #define CLK_AUD_LRCK_DETECT 2 278*4882a593Smuzhiyun #define CLK_AUD_I2S 3 279*4882a593Smuzhiyun #define CLK_AUD_APLL_TUNER 4 280*4882a593Smuzhiyun #define CLK_AUD_HDMI 5 281*4882a593Smuzhiyun #define CLK_AUD_SPDF 6 282*4882a593Smuzhiyun #define CLK_AUD_SPDF2 7 283*4882a593Smuzhiyun #define CLK_AUD_APLL 8 284*4882a593Smuzhiyun #define CLK_AUD_TML 9 285*4882a593Smuzhiyun #define CLK_AUD_AHB_IDLE_EXT 10 286*4882a593Smuzhiyun #define CLK_AUD_AHB_IDLE_INT 11 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define CLK_AUD_I2SIN1 12 289*4882a593Smuzhiyun #define CLK_AUD_I2SIN2 13 290*4882a593Smuzhiyun #define CLK_AUD_I2SIN3 14 291*4882a593Smuzhiyun #define CLK_AUD_I2SIN4 15 292*4882a593Smuzhiyun #define CLK_AUD_I2SIN5 16 293*4882a593Smuzhiyun #define CLK_AUD_I2SIN6 17 294*4882a593Smuzhiyun #define CLK_AUD_I2SO1 18 295*4882a593Smuzhiyun #define CLK_AUD_I2SO2 19 296*4882a593Smuzhiyun #define CLK_AUD_I2SO3 20 297*4882a593Smuzhiyun #define CLK_AUD_I2SO4 21 298*4882a593Smuzhiyun #define CLK_AUD_I2SO5 22 299*4882a593Smuzhiyun #define CLK_AUD_I2SO6 23 300*4882a593Smuzhiyun #define CLK_AUD_ASRCI1 24 301*4882a593Smuzhiyun #define CLK_AUD_ASRCI2 25 302*4882a593Smuzhiyun #define CLK_AUD_ASRCO1 26 303*4882a593Smuzhiyun #define CLK_AUD_ASRCO2 27 304*4882a593Smuzhiyun #define CLK_AUD_ASRC11 28 305*4882a593Smuzhiyun #define CLK_AUD_ASRC12 29 306*4882a593Smuzhiyun #define CLK_AUD_HDMIRX 30 307*4882a593Smuzhiyun #define CLK_AUD_INTDIR 31 308*4882a593Smuzhiyun #define CLK_AUD_A1SYS 32 309*4882a593Smuzhiyun #define CLK_AUD_A2SYS 33 310*4882a593Smuzhiyun #define CLK_AUD_AFE_CONN 34 311*4882a593Smuzhiyun #define CLK_AUD_AFE_PCMIF 35 312*4882a593Smuzhiyun #define CLK_AUD_AFE_MRGIF 36 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun #define CLK_AUD_MMIF_UL1 37 315*4882a593Smuzhiyun #define CLK_AUD_MMIF_UL2 38 316*4882a593Smuzhiyun #define CLK_AUD_MMIF_UL3 39 317*4882a593Smuzhiyun #define CLK_AUD_MMIF_UL4 40 318*4882a593Smuzhiyun #define CLK_AUD_MMIF_UL5 41 319*4882a593Smuzhiyun #define CLK_AUD_MMIF_UL6 42 320*4882a593Smuzhiyun #define CLK_AUD_MMIF_DL1 43 321*4882a593Smuzhiyun #define CLK_AUD_MMIF_DL2 44 322*4882a593Smuzhiyun #define CLK_AUD_MMIF_DL3 45 323*4882a593Smuzhiyun #define CLK_AUD_MMIF_DL4 46 324*4882a593Smuzhiyun #define CLK_AUD_MMIF_DL5 47 325*4882a593Smuzhiyun #define CLK_AUD_MMIF_DL6 48 326*4882a593Smuzhiyun #define CLK_AUD_MMIF_DLMCH 49 327*4882a593Smuzhiyun #define CLK_AUD_MMIF_ARB1 50 328*4882a593Smuzhiyun #define CLK_AUD_MMIF_AWB1 51 329*4882a593Smuzhiyun #define CLK_AUD_MMIF_AWB2 52 330*4882a593Smuzhiyun #define CLK_AUD_MMIF_DAI 53 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun #define CLK_AUD_DMIC1 54 333*4882a593Smuzhiyun #define CLK_AUD_DMIC2 55 334*4882a593Smuzhiyun #define CLK_AUD_ASRCI3 56 335*4882a593Smuzhiyun #define CLK_AUD_ASRCI4 57 336*4882a593Smuzhiyun #define CLK_AUD_ASRCI5 58 337*4882a593Smuzhiyun #define CLK_AUD_ASRCI6 59 338*4882a593Smuzhiyun #define CLK_AUD_ASRCO3 60 339*4882a593Smuzhiyun #define CLK_AUD_ASRCO4 61 340*4882a593Smuzhiyun #define CLK_AUD_ASRCO5 62 341*4882a593Smuzhiyun #define CLK_AUD_ASRCO6 63 342*4882a593Smuzhiyun #define CLK_AUD_MEM_ASRC1 64 343*4882a593Smuzhiyun #define CLK_AUD_MEM_ASRC2 65 344*4882a593Smuzhiyun #define CLK_AUD_MEM_ASRC3 66 345*4882a593Smuzhiyun #define CLK_AUD_MEM_ASRC4 67 346*4882a593Smuzhiyun #define CLK_AUD_MEM_ASRC5 68 347*4882a593Smuzhiyun #define CLK_AUD_DSD_ENC 69 348*4882a593Smuzhiyun #define CLK_AUD_ASRC_BRG 70 349*4882a593Smuzhiyun #define CLK_AUD_NR 71 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun /* MMSYS */ 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 1 354*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 2 355*4882a593Smuzhiyun #define CLK_MM_CMDQ 3 356*4882a593Smuzhiyun #define CLK_MM_MUTEX 4 357*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR 5 358*4882a593Smuzhiyun #define CLK_MM_DISP_BLS 6 359*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA 7 360*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA 8 361*4882a593Smuzhiyun #define CLK_MM_DISP_OVL 9 362*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP 10 363*4882a593Smuzhiyun #define CLK_MM_MDP_WROT 11 364*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA 12 365*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 13 366*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 14 367*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA 15 368*4882a593Smuzhiyun #define CLK_MM_MDP_BLS_26M 16 369*4882a593Smuzhiyun #define CLK_MM_CAM_MDP 17 370*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 18 371*4882a593Smuzhiyun #define CLK_MM_MUTEX_32K 19 372*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA1 20 373*4882a593Smuzhiyun #define CLK_MM_DISP_UFOE 21 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun #define CLK_MM_DSI_ENGINE 22 376*4882a593Smuzhiyun #define CLK_MM_DSI_DIG 23 377*4882a593Smuzhiyun #define CLK_MM_DPI_DIGL 24 378*4882a593Smuzhiyun #define CLK_MM_DPI_ENGINE 25 379*4882a593Smuzhiyun #define CLK_MM_DPI1_DIGL 26 380*4882a593Smuzhiyun #define CLK_MM_DPI1_ENGINE 27 381*4882a593Smuzhiyun #define CLK_MM_TVE_OUTPUT 28 382*4882a593Smuzhiyun #define CLK_MM_TVE_INPUT 29 383*4882a593Smuzhiyun #define CLK_MM_HDMI_PIXEL 30 384*4882a593Smuzhiyun #define CLK_MM_HDMI_PLL 31 385*4882a593Smuzhiyun #define CLK_MM_HDMI_AUDIO 32 386*4882a593Smuzhiyun #define CLK_MM_HDMI_SPDIF 33 387*4882a593Smuzhiyun #define CLK_MM_TVE_FMM 34 388*4882a593Smuzhiyun #define CLK_MM_NR 35 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun /* IMGSYS */ 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun #define CLK_IMG_SMI_COMM 1 393*4882a593Smuzhiyun #define CLK_IMG_RESZ 2 394*4882a593Smuzhiyun #define CLK_IMG_JPGDEC_SMI 3 395*4882a593Smuzhiyun #define CLK_IMG_JPGDEC 4 396*4882a593Smuzhiyun #define CLK_IMG_VENC_LT 5 397*4882a593Smuzhiyun #define CLK_IMG_VENC 6 398*4882a593Smuzhiyun #define CLK_IMG_NR 7 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun /* VDEC */ 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun #define CLK_VDEC_CKGEN 1 403*4882a593Smuzhiyun #define CLK_VDEC_LARB 2 404*4882a593Smuzhiyun #define CLK_VDEC_NR 3 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun /* HIFSYS */ 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun #define CLK_HIFSYS_USB0PHY 1 409*4882a593Smuzhiyun #define CLK_HIFSYS_USB1PHY 2 410*4882a593Smuzhiyun #define CLK_HIFSYS_PCIE0 3 411*4882a593Smuzhiyun #define CLK_HIFSYS_PCIE1 4 412*4882a593Smuzhiyun #define CLK_HIFSYS_PCIE2 5 413*4882a593Smuzhiyun #define CLK_HIFSYS_NR 6 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun /* ETHSYS */ 416*4882a593Smuzhiyun #define CLK_ETHSYS_HSDMA 1 417*4882a593Smuzhiyun #define CLK_ETHSYS_ESW 2 418*4882a593Smuzhiyun #define CLK_ETHSYS_GP2 3 419*4882a593Smuzhiyun #define CLK_ETHSYS_GP1 4 420*4882a593Smuzhiyun #define CLK_ETHSYS_PCM 5 421*4882a593Smuzhiyun #define CLK_ETHSYS_GDMA 6 422*4882a593Smuzhiyun #define CLK_ETHSYS_I2S 7 423*4882a593Smuzhiyun #define CLK_ETHSYS_CRYPTO 8 424*4882a593Smuzhiyun #define CLK_ETHSYS_NR 9 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun /* G3DSYS */ 427*4882a593Smuzhiyun #define CLK_G3DSYS_CORE 1 428*4882a593Smuzhiyun #define CLK_G3DSYS_NR 2 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun /* BDP */ 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun #define CLK_BDP_BRG_BA 1 433*4882a593Smuzhiyun #define CLK_BDP_BRG_DRAM 2 434*4882a593Smuzhiyun #define CLK_BDP_LARB_DRAM 3 435*4882a593Smuzhiyun #define CLK_BDP_WR_VDI_PXL 4 436*4882a593Smuzhiyun #define CLK_BDP_WR_VDI_DRAM 5 437*4882a593Smuzhiyun #define CLK_BDP_WR_B 6 438*4882a593Smuzhiyun #define CLK_BDP_DGI_IN 7 439*4882a593Smuzhiyun #define CLK_BDP_DGI_OUT 8 440*4882a593Smuzhiyun #define CLK_BDP_FMT_MAST_27 9 441*4882a593Smuzhiyun #define CLK_BDP_FMT_B 10 442*4882a593Smuzhiyun #define CLK_BDP_OSD_B 11 443*4882a593Smuzhiyun #define CLK_BDP_OSD_DRAM 12 444*4882a593Smuzhiyun #define CLK_BDP_OSD_AGENT 13 445*4882a593Smuzhiyun #define CLK_BDP_OSD_PXL 14 446*4882a593Smuzhiyun #define CLK_BDP_RLE_B 15 447*4882a593Smuzhiyun #define CLK_BDP_RLE_AGENT 16 448*4882a593Smuzhiyun #define CLK_BDP_RLE_DRAM 17 449*4882a593Smuzhiyun #define CLK_BDP_F27M 18 450*4882a593Smuzhiyun #define CLK_BDP_F27M_VDOUT 19 451*4882a593Smuzhiyun #define CLK_BDP_F27_74_74 20 452*4882a593Smuzhiyun #define CLK_BDP_F2FS 21 453*4882a593Smuzhiyun #define CLK_BDP_F2FS74_148 22 454*4882a593Smuzhiyun #define CLK_BDP_FB 23 455*4882a593Smuzhiyun #define CLK_BDP_VDO_DRAM 24 456*4882a593Smuzhiyun #define CLK_BDP_VDO_2FS 25 457*4882a593Smuzhiyun #define CLK_BDP_VDO_B 26 458*4882a593Smuzhiyun #define CLK_BDP_WR_DI_PXL 27 459*4882a593Smuzhiyun #define CLK_BDP_WR_DI_DRAM 28 460*4882a593Smuzhiyun #define CLK_BDP_WR_DI_B 29 461*4882a593Smuzhiyun #define CLK_BDP_NR_PXL 30 462*4882a593Smuzhiyun #define CLK_BDP_NR_DRAM 31 463*4882a593Smuzhiyun #define CLK_BDP_NR_B 32 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun #define CLK_BDP_RX_F 33 466*4882a593Smuzhiyun #define CLK_BDP_RX_X 34 467*4882a593Smuzhiyun #define CLK_BDP_RXPDT 35 468*4882a593Smuzhiyun #define CLK_BDP_RX_CSCL_N 36 469*4882a593Smuzhiyun #define CLK_BDP_RX_CSCL 37 470*4882a593Smuzhiyun #define CLK_BDP_RX_DDCSCL_N 38 471*4882a593Smuzhiyun #define CLK_BDP_RX_DDCSCL 39 472*4882a593Smuzhiyun #define CLK_BDP_RX_VCO 40 473*4882a593Smuzhiyun #define CLK_BDP_RX_DP 41 474*4882a593Smuzhiyun #define CLK_BDP_RX_P 42 475*4882a593Smuzhiyun #define CLK_BDP_RX_M 43 476*4882a593Smuzhiyun #define CLK_BDP_RX_PLL 44 477*4882a593Smuzhiyun #define CLK_BDP_BRG_RT_B 45 478*4882a593Smuzhiyun #define CLK_BDP_BRG_RT_DRAM 46 479*4882a593Smuzhiyun #define CLK_BDP_LARBRT_DRAM 47 480*4882a593Smuzhiyun #define CLK_BDP_TMDS_SYN 48 481*4882a593Smuzhiyun #define CLK_BDP_HDMI_MON 49 482*4882a593Smuzhiyun #define CLK_BDP_NR 50 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT2701_H */ 485