1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT6765_H 4*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT6765_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* FIX Clks */ 7*4882a593Smuzhiyun #define CLK_TOP_CLK26M 0 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* APMIXEDSYS */ 10*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL_L 0 11*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL 1 12*4882a593Smuzhiyun #define CLK_APMIXED_CCIPLL 2 13*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 3 14*4882a593Smuzhiyun #define CLK_APMIXED_MFGPLL 4 15*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 5 16*4882a593Smuzhiyun #define CLK_APMIXED_UNIV2PLL 6 17*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 7 18*4882a593Smuzhiyun #define CLK_APMIXED_APLL1 8 19*4882a593Smuzhiyun #define CLK_APMIXED_MPLL 9 20*4882a593Smuzhiyun #define CLK_APMIXED_ULPOSC1 10 21*4882a593Smuzhiyun #define CLK_APMIXED_ULPOSC2 11 22*4882a593Smuzhiyun #define CLK_APMIXED_SSUSB26M 12 23*4882a593Smuzhiyun #define CLK_APMIXED_APPLL26M 13 24*4882a593Smuzhiyun #define CLK_APMIXED_MIPIC0_26M 14 25*4882a593Smuzhiyun #define CLK_APMIXED_MDPLLGP26M 15 26*4882a593Smuzhiyun #define CLK_APMIXED_MMSYS_F26M 16 27*4882a593Smuzhiyun #define CLK_APMIXED_UFS26M 17 28*4882a593Smuzhiyun #define CLK_APMIXED_MIPIC1_26M 18 29*4882a593Smuzhiyun #define CLK_APMIXED_MEMPLL26M 19 30*4882a593Smuzhiyun #define CLK_APMIXED_CLKSQ_LVPLL_26M 20 31*4882a593Smuzhiyun #define CLK_APMIXED_MIPID0_26M 21 32*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 22 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* TOPCKGEN */ 35*4882a593Smuzhiyun #define CLK_TOP_SYSPLL 0 36*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 1 37*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D2 2 38*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D4 3 39*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D8 4 40*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D16 5 41*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3 6 42*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D2 7 43*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D4 8 44*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D8 9 45*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 10 46*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D2 11 47*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D4 12 48*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7 13 49*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D2 14 50*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D4 15 51*4882a593Smuzhiyun #define CLK_TOP_USB20_192M 16 52*4882a593Smuzhiyun #define CLK_TOP_USB20_192M_D4 17 53*4882a593Smuzhiyun #define CLK_TOP_USB20_192M_D8 18 54*4882a593Smuzhiyun #define CLK_TOP_USB20_192M_D16 19 55*4882a593Smuzhiyun #define CLK_TOP_USB20_192M_D32 20 56*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL 21 57*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 22 58*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 23 59*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 24 60*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 25 61*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 26 62*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 27 63*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 28 64*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D32 29 65*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 30 66*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D2 31 67*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D4 32 68*4882a593Smuzhiyun #define CLK_TOP_MMPLL 33 69*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D2 34 70*4882a593Smuzhiyun #define CLK_TOP_MPLL 35 71*4882a593Smuzhiyun #define CLK_TOP_DA_MPLL_104M_DIV 36 72*4882a593Smuzhiyun #define CLK_TOP_DA_MPLL_52M_DIV 37 73*4882a593Smuzhiyun #define CLK_TOP_MFGPLL 38 74*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL 39 75*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D2 40 76*4882a593Smuzhiyun #define CLK_TOP_APLL1 41 77*4882a593Smuzhiyun #define CLK_TOP_APLL1_D2 42 78*4882a593Smuzhiyun #define CLK_TOP_APLL1_D4 43 79*4882a593Smuzhiyun #define CLK_TOP_APLL1_D8 44 80*4882a593Smuzhiyun #define CLK_TOP_ULPOSC1 45 81*4882a593Smuzhiyun #define CLK_TOP_ULPOSC1_D2 46 82*4882a593Smuzhiyun #define CLK_TOP_ULPOSC1_D4 47 83*4882a593Smuzhiyun #define CLK_TOP_ULPOSC1_D8 48 84*4882a593Smuzhiyun #define CLK_TOP_ULPOSC1_D16 49 85*4882a593Smuzhiyun #define CLK_TOP_ULPOSC1_D32 50 86*4882a593Smuzhiyun #define CLK_TOP_DMPLL 51 87*4882a593Smuzhiyun #define CLK_TOP_F_FRTC 52 88*4882a593Smuzhiyun #define CLK_TOP_F_F26M 53 89*4882a593Smuzhiyun #define CLK_TOP_AXI 54 90*4882a593Smuzhiyun #define CLK_TOP_MM 55 91*4882a593Smuzhiyun #define CLK_TOP_SCP 56 92*4882a593Smuzhiyun #define CLK_TOP_MFG 57 93*4882a593Smuzhiyun #define CLK_TOP_F_FUART 58 94*4882a593Smuzhiyun #define CLK_TOP_SPI 59 95*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0 60 96*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1 61 97*4882a593Smuzhiyun #define CLK_TOP_AUDIO 62 98*4882a593Smuzhiyun #define CLK_TOP_AUD_1 63 99*4882a593Smuzhiyun #define CLK_TOP_AUD_ENGEN1 64 100*4882a593Smuzhiyun #define CLK_TOP_F_FDISP_PWM 65 101*4882a593Smuzhiyun #define CLK_TOP_SSPM 66 102*4882a593Smuzhiyun #define CLK_TOP_DXCC 67 103*4882a593Smuzhiyun #define CLK_TOP_I2C 68 104*4882a593Smuzhiyun #define CLK_TOP_F_FPWM 69 105*4882a593Smuzhiyun #define CLK_TOP_F_FSENINF 70 106*4882a593Smuzhiyun #define CLK_TOP_AES_FDE 71 107*4882a593Smuzhiyun #define CLK_TOP_F_BIST2FPC 72 108*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 109*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 110*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 111*4882a593Smuzhiyun #define CLK_TOP_DA_USB20_48M_DIV 76 112*4882a593Smuzhiyun #define CLK_TOP_DA_UNIV_48M_DIV 77 113*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV0 78 114*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV1 79 115*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV2 80 116*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV3 81 117*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 118*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 119*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 120*4882a593Smuzhiyun #define CLK_TOP_FMEM_OCC_DRC_EN 85 121*4882a593Smuzhiyun #define CLK_TOP_USB20_48M_EN 86 122*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_48M_EN 87 123*4882a593Smuzhiyun #define CLK_TOP_MPLL_104M_EN 88 124*4882a593Smuzhiyun #define CLK_TOP_MPLL_52M_EN 89 125*4882a593Smuzhiyun #define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 126*4882a593Smuzhiyun #define CLK_TOP_F_BIST2FPC_EN 91 127*4882a593Smuzhiyun #define CLK_TOP_MD_32K 92 128*4882a593Smuzhiyun #define CLK_TOP_MD_26M 93 129*4882a593Smuzhiyun #define CLK_TOP_MD2_32K 94 130*4882a593Smuzhiyun #define CLK_TOP_MD2_26M 95 131*4882a593Smuzhiyun #define CLK_TOP_AXI_SEL 96 132*4882a593Smuzhiyun #define CLK_TOP_MEM_SEL 97 133*4882a593Smuzhiyun #define CLK_TOP_MM_SEL 98 134*4882a593Smuzhiyun #define CLK_TOP_SCP_SEL 99 135*4882a593Smuzhiyun #define CLK_TOP_MFG_SEL 100 136*4882a593Smuzhiyun #define CLK_TOP_ATB_SEL 101 137*4882a593Smuzhiyun #define CLK_TOP_CAMTG_SEL 102 138*4882a593Smuzhiyun #define CLK_TOP_CAMTG1_SEL 103 139*4882a593Smuzhiyun #define CLK_TOP_CAMTG2_SEL 104 140*4882a593Smuzhiyun #define CLK_TOP_CAMTG3_SEL 105 141*4882a593Smuzhiyun #define CLK_TOP_UART_SEL 106 142*4882a593Smuzhiyun #define CLK_TOP_SPI_SEL 107 143*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_HCLK_SEL 108 144*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_SEL 109 145*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1_SEL 110 146*4882a593Smuzhiyun #define CLK_TOP_AUDIO_SEL 111 147*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS_SEL 112 148*4882a593Smuzhiyun #define CLK_TOP_AUD_1_SEL 113 149*4882a593Smuzhiyun #define CLK_TOP_AUD_ENGEN1_SEL 114 150*4882a593Smuzhiyun #define CLK_TOP_DISP_PWM_SEL 115 151*4882a593Smuzhiyun #define CLK_TOP_SSPM_SEL 116 152*4882a593Smuzhiyun #define CLK_TOP_DXCC_SEL 117 153*4882a593Smuzhiyun #define CLK_TOP_USB_TOP_SEL 118 154*4882a593Smuzhiyun #define CLK_TOP_SPM_SEL 119 155*4882a593Smuzhiyun #define CLK_TOP_I2C_SEL 120 156*4882a593Smuzhiyun #define CLK_TOP_PWM_SEL 121 157*4882a593Smuzhiyun #define CLK_TOP_SENINF_SEL 122 158*4882a593Smuzhiyun #define CLK_TOP_AES_FDE_SEL 123 159*4882a593Smuzhiyun #define CLK_TOP_PWRAP_ULPOSC_SEL 124 160*4882a593Smuzhiyun #define CLK_TOP_CAMTM_SEL 125 161*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 126 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* INFRACFG */ 164*4882a593Smuzhiyun #define CLK_IFR_ICUSB 0 165*4882a593Smuzhiyun #define CLK_IFR_GCE 1 166*4882a593Smuzhiyun #define CLK_IFR_THERM 2 167*4882a593Smuzhiyun #define CLK_IFR_I2C_AP 3 168*4882a593Smuzhiyun #define CLK_IFR_I2C_CCU 4 169*4882a593Smuzhiyun #define CLK_IFR_I2C_SSPM 5 170*4882a593Smuzhiyun #define CLK_IFR_I2C_RSV 6 171*4882a593Smuzhiyun #define CLK_IFR_PWM_HCLK 7 172*4882a593Smuzhiyun #define CLK_IFR_PWM1 8 173*4882a593Smuzhiyun #define CLK_IFR_PWM2 9 174*4882a593Smuzhiyun #define CLK_IFR_PWM3 10 175*4882a593Smuzhiyun #define CLK_IFR_PWM4 11 176*4882a593Smuzhiyun #define CLK_IFR_PWM5 12 177*4882a593Smuzhiyun #define CLK_IFR_PWM 13 178*4882a593Smuzhiyun #define CLK_IFR_UART0 14 179*4882a593Smuzhiyun #define CLK_IFR_UART1 15 180*4882a593Smuzhiyun #define CLK_IFR_GCE_26M 16 181*4882a593Smuzhiyun #define CLK_IFR_CQ_DMA_FPC 17 182*4882a593Smuzhiyun #define CLK_IFR_BTIF 18 183*4882a593Smuzhiyun #define CLK_IFR_SPI0 19 184*4882a593Smuzhiyun #define CLK_IFR_MSDC0 20 185*4882a593Smuzhiyun #define CLK_IFR_MSDC1 21 186*4882a593Smuzhiyun #define CLK_IFR_TRNG 22 187*4882a593Smuzhiyun #define CLK_IFR_AUXADC 23 188*4882a593Smuzhiyun #define CLK_IFR_CCIF1_AP 24 189*4882a593Smuzhiyun #define CLK_IFR_CCIF1_MD 25 190*4882a593Smuzhiyun #define CLK_IFR_AUXADC_MD 26 191*4882a593Smuzhiyun #define CLK_IFR_AP_DMA 27 192*4882a593Smuzhiyun #define CLK_IFR_DEVICE_APC 28 193*4882a593Smuzhiyun #define CLK_IFR_CCIF_AP 29 194*4882a593Smuzhiyun #define CLK_IFR_AUDIO 30 195*4882a593Smuzhiyun #define CLK_IFR_CCIF_MD 31 196*4882a593Smuzhiyun #define CLK_IFR_RG_PWM_FBCLK6 32 197*4882a593Smuzhiyun #define CLK_IFR_DISP_PWM 33 198*4882a593Smuzhiyun #define CLK_IFR_CLDMA_BCLK 34 199*4882a593Smuzhiyun #define CLK_IFR_AUDIO_26M_BCLK 35 200*4882a593Smuzhiyun #define CLK_IFR_SPI1 36 201*4882a593Smuzhiyun #define CLK_IFR_I2C4 37 202*4882a593Smuzhiyun #define CLK_IFR_SPI2 38 203*4882a593Smuzhiyun #define CLK_IFR_SPI3 39 204*4882a593Smuzhiyun #define CLK_IFR_I2C5 40 205*4882a593Smuzhiyun #define CLK_IFR_I2C5_ARBITER 41 206*4882a593Smuzhiyun #define CLK_IFR_I2C5_IMM 42 207*4882a593Smuzhiyun #define CLK_IFR_I2C1_ARBITER 43 208*4882a593Smuzhiyun #define CLK_IFR_I2C1_IMM 44 209*4882a593Smuzhiyun #define CLK_IFR_I2C2_ARBITER 45 210*4882a593Smuzhiyun #define CLK_IFR_I2C2_IMM 46 211*4882a593Smuzhiyun #define CLK_IFR_SPI4 47 212*4882a593Smuzhiyun #define CLK_IFR_SPI5 48 213*4882a593Smuzhiyun #define CLK_IFR_CQ_DMA 49 214*4882a593Smuzhiyun #define CLK_IFR_FAES_FDE 50 215*4882a593Smuzhiyun #define CLK_IFR_MSDC0_SELF 51 216*4882a593Smuzhiyun #define CLK_IFR_MSDC1_SELF 52 217*4882a593Smuzhiyun #define CLK_IFR_I2C6 53 218*4882a593Smuzhiyun #define CLK_IFR_AP_MSDC0 54 219*4882a593Smuzhiyun #define CLK_IFR_MD_MSDC0 55 220*4882a593Smuzhiyun #define CLK_IFR_MSDC0_SRC 56 221*4882a593Smuzhiyun #define CLK_IFR_MSDC1_SRC 57 222*4882a593Smuzhiyun #define CLK_IFR_AES_TOP0_BCLK 58 223*4882a593Smuzhiyun #define CLK_IFR_MCU_PM_BCLK 59 224*4882a593Smuzhiyun #define CLK_IFR_CCIF2_AP 60 225*4882a593Smuzhiyun #define CLK_IFR_CCIF2_MD 61 226*4882a593Smuzhiyun #define CLK_IFR_CCIF3_AP 62 227*4882a593Smuzhiyun #define CLK_IFR_CCIF3_MD 63 228*4882a593Smuzhiyun #define CLK_IFR_NR_CLK 64 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /* AUDIO */ 231*4882a593Smuzhiyun #define CLK_AUDIO_AFE 0 232*4882a593Smuzhiyun #define CLK_AUDIO_22M 1 233*4882a593Smuzhiyun #define CLK_AUDIO_APLL_TUNER 2 234*4882a593Smuzhiyun #define CLK_AUDIO_ADC 3 235*4882a593Smuzhiyun #define CLK_AUDIO_DAC 4 236*4882a593Smuzhiyun #define CLK_AUDIO_DAC_PREDIS 5 237*4882a593Smuzhiyun #define CLK_AUDIO_TML 6 238*4882a593Smuzhiyun #define CLK_AUDIO_I2S1_BCLK 7 239*4882a593Smuzhiyun #define CLK_AUDIO_I2S2_BCLK 8 240*4882a593Smuzhiyun #define CLK_AUDIO_I2S3_BCLK 9 241*4882a593Smuzhiyun #define CLK_AUDIO_I2S4_BCLK 10 242*4882a593Smuzhiyun #define CLK_AUDIO_NR_CLK 11 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* MIPI_RX_ANA_CSI0A */ 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define CLK_MIPI0A_CSR_CSI_EN_0A 0 247*4882a593Smuzhiyun #define CLK_MIPI0A_NR_CLK 1 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* MMSYS_CONFIG */ 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA0 0 252*4882a593Smuzhiyun #define CLK_MM_MDP_CCORR0 1 253*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 2 254*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 3 255*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP0 4 256*4882a593Smuzhiyun #define CLK_MM_MDP_WROT0 5 257*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA0 6 258*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0 7 259*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0_2L 8 260*4882a593Smuzhiyun #define CLK_MM_DISP_RSZ0 9 261*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA0 10 262*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA0 11 263*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR0 12 264*4882a593Smuzhiyun #define CLK_MM_DISP_CCORR0 13 265*4882a593Smuzhiyun #define CLK_MM_DISP_AAL0 14 266*4882a593Smuzhiyun #define CLK_MM_DISP_GAMMA0 15 267*4882a593Smuzhiyun #define CLK_MM_DISP_DITHER0 16 268*4882a593Smuzhiyun #define CLK_MM_DSI0 17 269*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 18 270*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 19 271*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 20 272*4882a593Smuzhiyun #define CLK_MM_SMI_COMM0 21 273*4882a593Smuzhiyun #define CLK_MM_SMI_COMM1 22 274*4882a593Smuzhiyun #define CLK_MM_CAM_MDP 23 275*4882a593Smuzhiyun #define CLK_MM_SMI_IMG 24 276*4882a593Smuzhiyun #define CLK_MM_SMI_CAM 25 277*4882a593Smuzhiyun #define CLK_MM_IMG_DL_RELAY 26 278*4882a593Smuzhiyun #define CLK_MM_IMG_DL_ASYNC_TOP 27 279*4882a593Smuzhiyun #define CLK_MM_DIG_DSI 28 280*4882a593Smuzhiyun #define CLK_MM_F26M_HRTWT 29 281*4882a593Smuzhiyun #define CLK_MM_NR_CLK 30 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun /* IMGSYS */ 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun #define CLK_IMG_LARB2 0 286*4882a593Smuzhiyun #define CLK_IMG_DIP 1 287*4882a593Smuzhiyun #define CLK_IMG_FDVT 2 288*4882a593Smuzhiyun #define CLK_IMG_DPE 3 289*4882a593Smuzhiyun #define CLK_IMG_RSC 4 290*4882a593Smuzhiyun #define CLK_IMG_NR_CLK 5 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* VENCSYS */ 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #define CLK_VENC_SET0_LARB 0 295*4882a593Smuzhiyun #define CLK_VENC_SET1_VENC 1 296*4882a593Smuzhiyun #define CLK_VENC_SET2_JPGENC 2 297*4882a593Smuzhiyun #define CLK_VENC_SET3_VDEC 3 298*4882a593Smuzhiyun #define CLK_VENC_NR_CLK 4 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* CAMSYS */ 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun #define CLK_CAM_LARB3 0 303*4882a593Smuzhiyun #define CLK_CAM_DFP_VAD 1 304*4882a593Smuzhiyun #define CLK_CAM 2 305*4882a593Smuzhiyun #define CLK_CAMTG 3 306*4882a593Smuzhiyun #define CLK_CAM_SENINF 4 307*4882a593Smuzhiyun #define CLK_CAMSV0 5 308*4882a593Smuzhiyun #define CLK_CAMSV1 6 309*4882a593Smuzhiyun #define CLK_CAMSV2 7 310*4882a593Smuzhiyun #define CLK_CAM_CCU 8 311*4882a593Smuzhiyun #define CLK_CAM_NR_CLK 9 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT6765_H */ 314