1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc. 4*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT8135_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT8135_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* TOPCKGEN */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_TOP_DSI0_LNTC_DSICLK 1 13*4882a593Smuzhiyun #define CLK_TOP_HDMITX_CLKDIG_CTS 2 14*4882a593Smuzhiyun #define CLK_TOP_CLKPH_MCK 3 15*4882a593Smuzhiyun #define CLK_TOP_CPUM_TCK_IN 4 16*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_806M 5 17*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_537P3M 6 18*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_322P4M 7 19*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_230P3M 8 20*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_624M 9 21*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_416M 10 22*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_249P6M 11 23*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_178P3M 12 24*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_48M 13 25*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D2 14 26*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D3 15 27*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D5 16 28*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D7 17 29*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D4 18 30*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D6 19 31*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 20 32*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D4 21 33*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D6 22 34*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D8 23 35*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D10 24 36*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D12 25 37*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D16 26 38*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D24 27 39*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3 28 40*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2P5 29 41*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 30 42*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3P5 31 43*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 32 44*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 33 45*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D6 34 46*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D8 35 47*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D10 36 48*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 37 49*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 38 50*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D6 39 51*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 40 52*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 41 53*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 42 54*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 43 55*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D10 44 56*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D26 45 57*4882a593Smuzhiyun #define CLK_TOP_APLL 46 58*4882a593Smuzhiyun #define CLK_TOP_APLL_D4 47 59*4882a593Smuzhiyun #define CLK_TOP_APLL_D8 48 60*4882a593Smuzhiyun #define CLK_TOP_APLL_D16 49 61*4882a593Smuzhiyun #define CLK_TOP_APLL_D24 50 62*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D2 51 63*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D4 52 64*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D8 53 65*4882a593Smuzhiyun #define CLK_TOP_LVDSTX_CLKDIG_CT 54 66*4882a593Smuzhiyun #define CLK_TOP_VPLL_DPIX 55 67*4882a593Smuzhiyun #define CLK_TOP_TVHDMI_H 56 68*4882a593Smuzhiyun #define CLK_TOP_HDMITX_CLKDIG_D2 57 69*4882a593Smuzhiyun #define CLK_TOP_HDMITX_CLKDIG_D3 58 70*4882a593Smuzhiyun #define CLK_TOP_TVHDMI_D2 59 71*4882a593Smuzhiyun #define CLK_TOP_TVHDMI_D4 60 72*4882a593Smuzhiyun #define CLK_TOP_MEMPLL_MCK_D4 61 73*4882a593Smuzhiyun #define CLK_TOP_AXI_SEL 62 74*4882a593Smuzhiyun #define CLK_TOP_SMI_SEL 63 75*4882a593Smuzhiyun #define CLK_TOP_MFG_SEL 64 76*4882a593Smuzhiyun #define CLK_TOP_IRDA_SEL 65 77*4882a593Smuzhiyun #define CLK_TOP_CAM_SEL 66 78*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS_SEL 67 79*4882a593Smuzhiyun #define CLK_TOP_JPG_SEL 68 80*4882a593Smuzhiyun #define CLK_TOP_DISP_SEL 69 81*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1_SEL 70 82*4882a593Smuzhiyun #define CLK_TOP_MSDC30_2_SEL 71 83*4882a593Smuzhiyun #define CLK_TOP_MSDC30_3_SEL 72 84*4882a593Smuzhiyun #define CLK_TOP_MSDC30_4_SEL 73 85*4882a593Smuzhiyun #define CLK_TOP_USB20_SEL 74 86*4882a593Smuzhiyun #define CLK_TOP_VENC_SEL 75 87*4882a593Smuzhiyun #define CLK_TOP_SPI_SEL 76 88*4882a593Smuzhiyun #define CLK_TOP_UART_SEL 77 89*4882a593Smuzhiyun #define CLK_TOP_MEM_SEL 78 90*4882a593Smuzhiyun #define CLK_TOP_CAMTG_SEL 79 91*4882a593Smuzhiyun #define CLK_TOP_AUDIO_SEL 80 92*4882a593Smuzhiyun #define CLK_TOP_FIX_SEL 81 93*4882a593Smuzhiyun #define CLK_TOP_VDEC_SEL 82 94*4882a593Smuzhiyun #define CLK_TOP_DDRPHYCFG_SEL 83 95*4882a593Smuzhiyun #define CLK_TOP_DPILVDS_SEL 84 96*4882a593Smuzhiyun #define CLK_TOP_PMICSPI_SEL 85 97*4882a593Smuzhiyun #define CLK_TOP_MSDC30_0_SEL 86 98*4882a593Smuzhiyun #define CLK_TOP_SMI_MFG_AS_SEL 87 99*4882a593Smuzhiyun #define CLK_TOP_GCPU_SEL 88 100*4882a593Smuzhiyun #define CLK_TOP_DPI1_SEL 89 101*4882a593Smuzhiyun #define CLK_TOP_CCI_SEL 90 102*4882a593Smuzhiyun #define CLK_TOP_APLL_SEL 91 103*4882a593Smuzhiyun #define CLK_TOP_HDMIPLL_SEL 92 104*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 93 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* APMIXED_SYS */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL1 1 109*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL2 2 110*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 3 111*4882a593Smuzhiyun #define CLK_APMIXED_UNIVPLL 4 112*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 5 113*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 6 114*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL 7 115*4882a593Smuzhiyun #define CLK_APMIXED_LVDSPLL 8 116*4882a593Smuzhiyun #define CLK_APMIXED_AUDPLL 9 117*4882a593Smuzhiyun #define CLK_APMIXED_VDECPLL 10 118*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 11 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* INFRA_SYS */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define CLK_INFRA_PMIC_WRAP 1 123*4882a593Smuzhiyun #define CLK_INFRA_PMICSPI 2 124*4882a593Smuzhiyun #define CLK_INFRA_CCIF1_AP_CTRL 3 125*4882a593Smuzhiyun #define CLK_INFRA_CCIF0_AP_CTRL 4 126*4882a593Smuzhiyun #define CLK_INFRA_KP 5 127*4882a593Smuzhiyun #define CLK_INFRA_CPUM 6 128*4882a593Smuzhiyun #define CLK_INFRA_M4U 7 129*4882a593Smuzhiyun #define CLK_INFRA_MFGAXI 8 130*4882a593Smuzhiyun #define CLK_INFRA_DEVAPC 9 131*4882a593Smuzhiyun #define CLK_INFRA_AUDIO 10 132*4882a593Smuzhiyun #define CLK_INFRA_MFG_BUS 11 133*4882a593Smuzhiyun #define CLK_INFRA_SMI 12 134*4882a593Smuzhiyun #define CLK_INFRA_DBGCLK 13 135*4882a593Smuzhiyun #define CLK_INFRA_NR_CLK 14 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* PERI_SYS */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define CLK_PERI_I2C5 1 140*4882a593Smuzhiyun #define CLK_PERI_I2C4 2 141*4882a593Smuzhiyun #define CLK_PERI_I2C3 3 142*4882a593Smuzhiyun #define CLK_PERI_I2C2 4 143*4882a593Smuzhiyun #define CLK_PERI_I2C1 5 144*4882a593Smuzhiyun #define CLK_PERI_I2C0 6 145*4882a593Smuzhiyun #define CLK_PERI_UART3 7 146*4882a593Smuzhiyun #define CLK_PERI_UART2 8 147*4882a593Smuzhiyun #define CLK_PERI_UART1 9 148*4882a593Smuzhiyun #define CLK_PERI_UART0 10 149*4882a593Smuzhiyun #define CLK_PERI_IRDA 11 150*4882a593Smuzhiyun #define CLK_PERI_NLI 12 151*4882a593Smuzhiyun #define CLK_PERI_MD_HIF 13 152*4882a593Smuzhiyun #define CLK_PERI_AP_HIF 14 153*4882a593Smuzhiyun #define CLK_PERI_MSDC30_3 15 154*4882a593Smuzhiyun #define CLK_PERI_MSDC30_2 16 155*4882a593Smuzhiyun #define CLK_PERI_MSDC30_1 17 156*4882a593Smuzhiyun #define CLK_PERI_MSDC20_2 18 157*4882a593Smuzhiyun #define CLK_PERI_MSDC20_1 19 158*4882a593Smuzhiyun #define CLK_PERI_AP_DMA 20 159*4882a593Smuzhiyun #define CLK_PERI_USB1 21 160*4882a593Smuzhiyun #define CLK_PERI_USB0 22 161*4882a593Smuzhiyun #define CLK_PERI_PWM 23 162*4882a593Smuzhiyun #define CLK_PERI_PWM7 24 163*4882a593Smuzhiyun #define CLK_PERI_PWM6 25 164*4882a593Smuzhiyun #define CLK_PERI_PWM5 26 165*4882a593Smuzhiyun #define CLK_PERI_PWM4 27 166*4882a593Smuzhiyun #define CLK_PERI_PWM3 28 167*4882a593Smuzhiyun #define CLK_PERI_PWM2 29 168*4882a593Smuzhiyun #define CLK_PERI_PWM1 30 169*4882a593Smuzhiyun #define CLK_PERI_THERM 31 170*4882a593Smuzhiyun #define CLK_PERI_NFI 32 171*4882a593Smuzhiyun #define CLK_PERI_USBSLV 33 172*4882a593Smuzhiyun #define CLK_PERI_USB1_MCU 34 173*4882a593Smuzhiyun #define CLK_PERI_USB0_MCU 35 174*4882a593Smuzhiyun #define CLK_PERI_GCPU 36 175*4882a593Smuzhiyun #define CLK_PERI_FHCTL 37 176*4882a593Smuzhiyun #define CLK_PERI_SPI1 38 177*4882a593Smuzhiyun #define CLK_PERI_AUXADC 39 178*4882a593Smuzhiyun #define CLK_PERI_PERI_PWRAP 40 179*4882a593Smuzhiyun #define CLK_PERI_I2C6 41 180*4882a593Smuzhiyun #define CLK_PERI_UART0_SEL 42 181*4882a593Smuzhiyun #define CLK_PERI_UART1_SEL 43 182*4882a593Smuzhiyun #define CLK_PERI_UART2_SEL 44 183*4882a593Smuzhiyun #define CLK_PERI_UART3_SEL 45 184*4882a593Smuzhiyun #define CLK_PERI_NR_CLK 46 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT8135_H */ 187