1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 MediaTek Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT7629_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT7629_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* TOPCKGEN */ 10*4882a593Smuzhiyun #define CLK_TOP_TO_U2_PHY 0 11*4882a593Smuzhiyun #define CLK_TOP_TO_U2_PHY_1P 1 12*4882a593Smuzhiyun #define CLK_TOP_PCIE0_PIPE_EN 2 13*4882a593Smuzhiyun #define CLK_TOP_PCIE1_PIPE_EN 3 14*4882a593Smuzhiyun #define CLK_TOP_SSUSB_TX250M 4 15*4882a593Smuzhiyun #define CLK_TOP_SSUSB_EQ_RX250M 5 16*4882a593Smuzhiyun #define CLK_TOP_SSUSB_CDR_REF 6 17*4882a593Smuzhiyun #define CLK_TOP_SSUSB_CDR_FB 7 18*4882a593Smuzhiyun #define CLK_TOP_SATA_ASIC 8 19*4882a593Smuzhiyun #define CLK_TOP_SATA_RBC 9 20*4882a593Smuzhiyun #define CLK_TOP_TO_USB3_SYS 10 21*4882a593Smuzhiyun #define CLK_TOP_P1_1MHZ 11 22*4882a593Smuzhiyun #define CLK_TOP_4MHZ 12 23*4882a593Smuzhiyun #define CLK_TOP_P0_1MHZ 13 24*4882a593Smuzhiyun #define CLK_TOP_ETH_500M 14 25*4882a593Smuzhiyun #define CLK_TOP_TXCLK_SRC_PRE 15 26*4882a593Smuzhiyun #define CLK_TOP_RTC 16 27*4882a593Smuzhiyun #define CLK_TOP_PWM_QTR_26M 17 28*4882a593Smuzhiyun #define CLK_TOP_CPUM_TCK_IN 18 29*4882a593Smuzhiyun #define CLK_TOP_TO_USB3_DA_TOP 19 30*4882a593Smuzhiyun #define CLK_TOP_MEMPLL 20 31*4882a593Smuzhiyun #define CLK_TOP_DMPLL 21 32*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D4 22 33*4882a593Smuzhiyun #define CLK_TOP_DMPLL_D8 23 34*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 24 35*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D2 25 36*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D4 26 37*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D8 27 38*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D16 28 39*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D2 29 40*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D4 30 41*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D8 31 42*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 32 43*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D2 33 44*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D4 34 45*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7 35 46*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D2 36 47*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D4 37 48*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D16 38 49*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL 39 50*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 40 51*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 41 52*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D8 42 53*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 43 54*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 44 55*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 45 56*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 46 57*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D16 47 58*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 48 59*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D2 49 60*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D4 50 61*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D16 51 62*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 52 63*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D80_D4 53 64*4882a593Smuzhiyun #define CLK_TOP_UNIV48M 54 65*4882a593Smuzhiyun #define CLK_TOP_SGMIIPLL_D2 55 66*4882a593Smuzhiyun #define CLK_TOP_CLKXTAL_D4 56 67*4882a593Smuzhiyun #define CLK_TOP_HD_FAXI 57 68*4882a593Smuzhiyun #define CLK_TOP_FAXI 58 69*4882a593Smuzhiyun #define CLK_TOP_F_FAUD_INTBUS 59 70*4882a593Smuzhiyun #define CLK_TOP_AP2WBHIF_HCLK 60 71*4882a593Smuzhiyun #define CLK_TOP_10M_INFRAO 61 72*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1 62 73*4882a593Smuzhiyun #define CLK_TOP_SPI 63 74*4882a593Smuzhiyun #define CLK_TOP_SF 64 75*4882a593Smuzhiyun #define CLK_TOP_FLASH 65 76*4882a593Smuzhiyun #define CLK_TOP_TO_USB3_REF 66 77*4882a593Smuzhiyun #define CLK_TOP_TO_USB3_MCU 67 78*4882a593Smuzhiyun #define CLK_TOP_TO_USB3_DMA 68 79*4882a593Smuzhiyun #define CLK_TOP_FROM_TOP_AHB 69 80*4882a593Smuzhiyun #define CLK_TOP_FROM_TOP_AXI 70 81*4882a593Smuzhiyun #define CLK_TOP_PCIE1_MAC_EN 71 82*4882a593Smuzhiyun #define CLK_TOP_PCIE0_MAC_EN 72 83*4882a593Smuzhiyun #define CLK_TOP_AXI_SEL 73 84*4882a593Smuzhiyun #define CLK_TOP_MEM_SEL 74 85*4882a593Smuzhiyun #define CLK_TOP_DDRPHYCFG_SEL 75 86*4882a593Smuzhiyun #define CLK_TOP_ETH_SEL 76 87*4882a593Smuzhiyun #define CLK_TOP_PWM_SEL 77 88*4882a593Smuzhiyun #define CLK_TOP_F10M_REF_SEL 78 89*4882a593Smuzhiyun #define CLK_TOP_NFI_INFRA_SEL 79 90*4882a593Smuzhiyun #define CLK_TOP_FLASH_SEL 80 91*4882a593Smuzhiyun #define CLK_TOP_UART_SEL 81 92*4882a593Smuzhiyun #define CLK_TOP_SPI0_SEL 82 93*4882a593Smuzhiyun #define CLK_TOP_SPI1_SEL 83 94*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_SEL 84 95*4882a593Smuzhiyun #define CLK_TOP_MSDC30_0_SEL 85 96*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1_SEL 86 97*4882a593Smuzhiyun #define CLK_TOP_AP2WBMCU_SEL 87 98*4882a593Smuzhiyun #define CLK_TOP_AP2WBHIF_SEL 88 99*4882a593Smuzhiyun #define CLK_TOP_AUDIO_SEL 89 100*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS_SEL 90 101*4882a593Smuzhiyun #define CLK_TOP_PMICSPI_SEL 91 102*4882a593Smuzhiyun #define CLK_TOP_SCP_SEL 92 103*4882a593Smuzhiyun #define CLK_TOP_ATB_SEL 93 104*4882a593Smuzhiyun #define CLK_TOP_HIF_SEL 94 105*4882a593Smuzhiyun #define CLK_TOP_SATA_SEL 95 106*4882a593Smuzhiyun #define CLK_TOP_U2_SEL 96 107*4882a593Smuzhiyun #define CLK_TOP_AUD1_SEL 97 108*4882a593Smuzhiyun #define CLK_TOP_AUD2_SEL 98 109*4882a593Smuzhiyun #define CLK_TOP_IRRX_SEL 99 110*4882a593Smuzhiyun #define CLK_TOP_IRTX_SEL 100 111*4882a593Smuzhiyun #define CLK_TOP_SATA_MCU_SEL 101 112*4882a593Smuzhiyun #define CLK_TOP_PCIE0_MCU_SEL 102 113*4882a593Smuzhiyun #define CLK_TOP_PCIE1_MCU_SEL 103 114*4882a593Smuzhiyun #define CLK_TOP_SSUSB_MCU_SEL 104 115*4882a593Smuzhiyun #define CLK_TOP_CRYPTO_SEL 105 116*4882a593Smuzhiyun #define CLK_TOP_SGMII_REF_1_SEL 106 117*4882a593Smuzhiyun #define CLK_TOP_10M_SEL 107 118*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 108 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* INFRACFG */ 121*4882a593Smuzhiyun #define CLK_INFRA_MUX1_SEL 0 122*4882a593Smuzhiyun #define CLK_INFRA_DBGCLK_PD 1 123*4882a593Smuzhiyun #define CLK_INFRA_TRNG_PD 2 124*4882a593Smuzhiyun #define CLK_INFRA_DEVAPC_PD 3 125*4882a593Smuzhiyun #define CLK_INFRA_APXGPT_PD 4 126*4882a593Smuzhiyun #define CLK_INFRA_SEJ_PD 5 127*4882a593Smuzhiyun #define CLK_INFRA_NR_CLK 6 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* PERICFG */ 130*4882a593Smuzhiyun #define CLK_PERIBUS_SEL 0 131*4882a593Smuzhiyun #define CLK_PERI_PWM1_PD 1 132*4882a593Smuzhiyun #define CLK_PERI_PWM2_PD 2 133*4882a593Smuzhiyun #define CLK_PERI_PWM3_PD 3 134*4882a593Smuzhiyun #define CLK_PERI_PWM4_PD 4 135*4882a593Smuzhiyun #define CLK_PERI_PWM5_PD 5 136*4882a593Smuzhiyun #define CLK_PERI_PWM6_PD 6 137*4882a593Smuzhiyun #define CLK_PERI_PWM7_PD 7 138*4882a593Smuzhiyun #define CLK_PERI_PWM_PD 8 139*4882a593Smuzhiyun #define CLK_PERI_AP_DMA_PD 9 140*4882a593Smuzhiyun #define CLK_PERI_MSDC30_1_PD 10 141*4882a593Smuzhiyun #define CLK_PERI_UART0_PD 11 142*4882a593Smuzhiyun #define CLK_PERI_UART1_PD 12 143*4882a593Smuzhiyun #define CLK_PERI_UART2_PD 13 144*4882a593Smuzhiyun #define CLK_PERI_UART3_PD 14 145*4882a593Smuzhiyun #define CLK_PERI_BTIF_PD 15 146*4882a593Smuzhiyun #define CLK_PERI_I2C0_PD 16 147*4882a593Smuzhiyun #define CLK_PERI_SPI0_PD 17 148*4882a593Smuzhiyun #define CLK_PERI_SNFI_PD 18 149*4882a593Smuzhiyun #define CLK_PERI_NFI_PD 19 150*4882a593Smuzhiyun #define CLK_PERI_NFIECC_PD 20 151*4882a593Smuzhiyun #define CLK_PERI_FLASH_PD 21 152*4882a593Smuzhiyun #define CLK_PERI_NR_CLK 22 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* APMIXEDSYS */ 155*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL 0 156*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 1 157*4882a593Smuzhiyun #define CLK_APMIXED_UNIV2PLL 2 158*4882a593Smuzhiyun #define CLK_APMIXED_ETH1PLL 3 159*4882a593Smuzhiyun #define CLK_APMIXED_ETH2PLL 4 160*4882a593Smuzhiyun #define CLK_APMIXED_SGMIPLL 5 161*4882a593Smuzhiyun #define CLK_APMIXED_MAIN_CORE_EN 6 162*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 7 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* SSUSBSYS */ 165*4882a593Smuzhiyun #define CLK_SSUSB_U2_PHY_1P_EN 0 166*4882a593Smuzhiyun #define CLK_SSUSB_U2_PHY_EN 1 167*4882a593Smuzhiyun #define CLK_SSUSB_REF_EN 2 168*4882a593Smuzhiyun #define CLK_SSUSB_SYS_EN 3 169*4882a593Smuzhiyun #define CLK_SSUSB_MCU_EN 4 170*4882a593Smuzhiyun #define CLK_SSUSB_DMA_EN 5 171*4882a593Smuzhiyun #define CLK_SSUSB_NR_CLK 6 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun /* PCIESYS */ 174*4882a593Smuzhiyun #define CLK_PCIE_P1_AUX_EN 0 175*4882a593Smuzhiyun #define CLK_PCIE_P1_OBFF_EN 1 176*4882a593Smuzhiyun #define CLK_PCIE_P1_AHB_EN 2 177*4882a593Smuzhiyun #define CLK_PCIE_P1_AXI_EN 3 178*4882a593Smuzhiyun #define CLK_PCIE_P1_MAC_EN 4 179*4882a593Smuzhiyun #define CLK_PCIE_P1_PIPE_EN 5 180*4882a593Smuzhiyun #define CLK_PCIE_P0_AUX_EN 6 181*4882a593Smuzhiyun #define CLK_PCIE_P0_OBFF_EN 7 182*4882a593Smuzhiyun #define CLK_PCIE_P0_AHB_EN 8 183*4882a593Smuzhiyun #define CLK_PCIE_P0_AXI_EN 9 184*4882a593Smuzhiyun #define CLK_PCIE_P0_MAC_EN 10 185*4882a593Smuzhiyun #define CLK_PCIE_P0_PIPE_EN 11 186*4882a593Smuzhiyun #define CLK_PCIE_NR_CLK 12 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* ETHSYS */ 189*4882a593Smuzhiyun #define CLK_ETH_FE_EN 0 190*4882a593Smuzhiyun #define CLK_ETH_GP2_EN 1 191*4882a593Smuzhiyun #define CLK_ETH_GP1_EN 2 192*4882a593Smuzhiyun #define CLK_ETH_GP0_EN 3 193*4882a593Smuzhiyun #define CLK_ETH_ESW_EN 4 194*4882a593Smuzhiyun #define CLK_ETH_NR_CLK 5 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* SGMIISYS */ 197*4882a593Smuzhiyun #define CLK_SGMII_TX_EN 0 198*4882a593Smuzhiyun #define CLK_SGMII_RX_EN 1 199*4882a593Smuzhiyun #define CLK_SGMII_CDR_REF 2 200*4882a593Smuzhiyun #define CLK_SGMII_CDR_FB 3 201*4882a593Smuzhiyun #define CLK_SGMII_NR_CLK 4 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT7629_H */ 204