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Searched refs:CLK_TOP_AUD_INTBUS_SEL (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt8135-clk.h78 #define CLK_TOP_AUD_INTBUS_SEL 67 macro
H A Dmt7629-clk.h100 #define CLK_TOP_AUD_INTBUS_SEL 90 macro
H A Dmt8516-clk.h168 #define CLK_TOP_AUD_INTBUS_SEL 136 macro
H A Dmt7622-clk.h85 #define CLK_TOP_AUD_INTBUS_SEL 73 macro
H A Dmt6765-clk.h147 #define CLK_TOP_AUD_INTBUS_SEL 112 macro
H A Dmt8173-clk.h111 #define CLK_TOP_AUD_INTBUS_SEL 101 macro
H A Dmt2712-clk.h148 #define CLK_TOP_AUD_INTBUS_SEL 117 macro
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt8135.c359 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt7629.c525 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt7622.c557 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8516.c377 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8167.c549 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8173.c565 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
H A Dclk-mt6765.c419 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
H A Dclk-mt2712.c778 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi798 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,