1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre, SAS. 5*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT8516_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT8516_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* APMIXEDSYS */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL 0 14*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 1 15*4882a593Smuzhiyun #define CLK_APMIXED_UNIVPLL 2 16*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 3 17*4882a593Smuzhiyun #define CLK_APMIXED_APLL1 4 18*4882a593Smuzhiyun #define CLK_APMIXED_APLL2 5 19*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 6 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* INFRACFG */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CLK_IFR_MUX1_SEL 0 24*4882a593Smuzhiyun #define CLK_IFR_ETH_25M_SEL 1 25*4882a593Smuzhiyun #define CLK_IFR_I2C0_SEL 2 26*4882a593Smuzhiyun #define CLK_IFR_I2C1_SEL 3 27*4882a593Smuzhiyun #define CLK_IFR_I2C2_SEL 4 28*4882a593Smuzhiyun #define CLK_IFR_NR_CLK 5 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* TOPCKGEN */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define CLK_TOP_CLK_NULL 0 33*4882a593Smuzhiyun #define CLK_TOP_I2S_INFRA_BCK 1 34*4882a593Smuzhiyun #define CLK_TOP_MEMPLL 2 35*4882a593Smuzhiyun #define CLK_TOP_DMPLL 3 36*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D2 4 37*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D4 5 38*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D8 6 39*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D16 7 40*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D11 8 41*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D22 9 42*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D3 10 43*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D6 11 44*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D12 12 45*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D5 13 46*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D10 14 47*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D20 15 48*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D40 16 49*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D7 17 50*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D14 18 51*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 19 52*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D4 20 53*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D8 21 54*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D16 22 55*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 23 56*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D6 24 57*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D12 25 58*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D24 26 59*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 27 60*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D20 28 61*4882a593Smuzhiyun #define CLK_TOP_MMPLL380M 29 62*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D2 30 63*4882a593Smuzhiyun #define CLK_TOP_MMPLL_200M 31 64*4882a593Smuzhiyun #define CLK_TOP_USB_PHY48M 32 65*4882a593Smuzhiyun #define CLK_TOP_APLL1 33 66*4882a593Smuzhiyun #define CLK_TOP_APLL1_D2 34 67*4882a593Smuzhiyun #define CLK_TOP_APLL1_D4 35 68*4882a593Smuzhiyun #define CLK_TOP_APLL1_D8 36 69*4882a593Smuzhiyun #define CLK_TOP_APLL2 37 70*4882a593Smuzhiyun #define CLK_TOP_APLL2_D2 38 71*4882a593Smuzhiyun #define CLK_TOP_APLL2_D4 39 72*4882a593Smuzhiyun #define CLK_TOP_APLL2_D8 40 73*4882a593Smuzhiyun #define CLK_TOP_CLK26M 41 74*4882a593Smuzhiyun #define CLK_TOP_CLK26M_D2 42 75*4882a593Smuzhiyun #define CLK_TOP_AHB_INFRA_D2 43 76*4882a593Smuzhiyun #define CLK_TOP_NFI1X 44 77*4882a593Smuzhiyun #define CLK_TOP_ETH_D2 45 78*4882a593Smuzhiyun #define CLK_TOP_THEM 46 79*4882a593Smuzhiyun #define CLK_TOP_APDMA 47 80*4882a593Smuzhiyun #define CLK_TOP_I2C0 48 81*4882a593Smuzhiyun #define CLK_TOP_I2C1 49 82*4882a593Smuzhiyun #define CLK_TOP_AUXADC1 50 83*4882a593Smuzhiyun #define CLK_TOP_NFI 51 84*4882a593Smuzhiyun #define CLK_TOP_NFIECC 52 85*4882a593Smuzhiyun #define CLK_TOP_DEBUGSYS 53 86*4882a593Smuzhiyun #define CLK_TOP_PWM 54 87*4882a593Smuzhiyun #define CLK_TOP_UART0 55 88*4882a593Smuzhiyun #define CLK_TOP_UART1 56 89*4882a593Smuzhiyun #define CLK_TOP_BTIF 57 90*4882a593Smuzhiyun #define CLK_TOP_USB 58 91*4882a593Smuzhiyun #define CLK_TOP_FLASHIF_26M 59 92*4882a593Smuzhiyun #define CLK_TOP_AUXADC2 60 93*4882a593Smuzhiyun #define CLK_TOP_I2C2 61 94*4882a593Smuzhiyun #define CLK_TOP_MSDC0 62 95*4882a593Smuzhiyun #define CLK_TOP_MSDC1 63 96*4882a593Smuzhiyun #define CLK_TOP_NFI2X 64 97*4882a593Smuzhiyun #define CLK_TOP_PMICWRAP_AP 65 98*4882a593Smuzhiyun #define CLK_TOP_SEJ 66 99*4882a593Smuzhiyun #define CLK_TOP_MEMSLP_DLYER 67 100*4882a593Smuzhiyun #define CLK_TOP_SPI 68 101*4882a593Smuzhiyun #define CLK_TOP_APXGPT 69 102*4882a593Smuzhiyun #define CLK_TOP_AUDIO 70 103*4882a593Smuzhiyun #define CLK_TOP_PMICWRAP_MD 71 104*4882a593Smuzhiyun #define CLK_TOP_PMICWRAP_CONN 72 105*4882a593Smuzhiyun #define CLK_TOP_PMICWRAP_26M 73 106*4882a593Smuzhiyun #define CLK_TOP_AUX_ADC 74 107*4882a593Smuzhiyun #define CLK_TOP_AUX_TP 75 108*4882a593Smuzhiyun #define CLK_TOP_MSDC2 76 109*4882a593Smuzhiyun #define CLK_TOP_RBIST 77 110*4882a593Smuzhiyun #define CLK_TOP_NFI_BUS 78 111*4882a593Smuzhiyun #define CLK_TOP_GCE 79 112*4882a593Smuzhiyun #define CLK_TOP_TRNG 80 113*4882a593Smuzhiyun #define CLK_TOP_SEJ_13M 81 114*4882a593Smuzhiyun #define CLK_TOP_AES 82 115*4882a593Smuzhiyun #define CLK_TOP_PWM_B 83 116*4882a593Smuzhiyun #define CLK_TOP_PWM1_FB 84 117*4882a593Smuzhiyun #define CLK_TOP_PWM2_FB 85 118*4882a593Smuzhiyun #define CLK_TOP_PWM3_FB 86 119*4882a593Smuzhiyun #define CLK_TOP_PWM4_FB 87 120*4882a593Smuzhiyun #define CLK_TOP_PWM5_FB 88 121*4882a593Smuzhiyun #define CLK_TOP_USB_1P 89 122*4882a593Smuzhiyun #define CLK_TOP_FLASHIF_FREERUN 90 123*4882a593Smuzhiyun #define CLK_TOP_66M_ETH 91 124*4882a593Smuzhiyun #define CLK_TOP_133M_ETH 92 125*4882a593Smuzhiyun #define CLK_TOP_FETH_25M 93 126*4882a593Smuzhiyun #define CLK_TOP_FETH_50M 94 127*4882a593Smuzhiyun #define CLK_TOP_FLASHIF_AXI 95 128*4882a593Smuzhiyun #define CLK_TOP_USBIF 96 129*4882a593Smuzhiyun #define CLK_TOP_UART2 97 130*4882a593Smuzhiyun #define CLK_TOP_BSI 98 131*4882a593Smuzhiyun #define CLK_TOP_RG_SPINOR 99 132*4882a593Smuzhiyun #define CLK_TOP_RG_MSDC2 100 133*4882a593Smuzhiyun #define CLK_TOP_RG_ETH 101 134*4882a593Smuzhiyun #define CLK_TOP_RG_AUD1 102 135*4882a593Smuzhiyun #define CLK_TOP_RG_AUD2 103 136*4882a593Smuzhiyun #define CLK_TOP_RG_AUD_ENGEN1 104 137*4882a593Smuzhiyun #define CLK_TOP_RG_AUD_ENGEN2 105 138*4882a593Smuzhiyun #define CLK_TOP_RG_I2C 106 139*4882a593Smuzhiyun #define CLK_TOP_RG_PWM_INFRA 107 140*4882a593Smuzhiyun #define CLK_TOP_RG_AUD_SPDIF_IN 108 141*4882a593Smuzhiyun #define CLK_TOP_RG_UART2 109 142*4882a593Smuzhiyun #define CLK_TOP_RG_BSI 110 143*4882a593Smuzhiyun #define CLK_TOP_RG_DBG_ATCLK 111 144*4882a593Smuzhiyun #define CLK_TOP_RG_NFIECC 112 145*4882a593Smuzhiyun #define CLK_TOP_RG_APLL1_D2_EN 113 146*4882a593Smuzhiyun #define CLK_TOP_RG_APLL1_D4_EN 114 147*4882a593Smuzhiyun #define CLK_TOP_RG_APLL1_D8_EN 115 148*4882a593Smuzhiyun #define CLK_TOP_RG_APLL2_D2_EN 116 149*4882a593Smuzhiyun #define CLK_TOP_RG_APLL2_D4_EN 117 150*4882a593Smuzhiyun #define CLK_TOP_RG_APLL2_D8_EN 118 151*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV0 119 152*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV1 120 153*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV2 121 154*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV3 122 155*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV4 123 156*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV4B 124 157*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV5 125 158*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV5B 126 159*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV6 127 160*4882a593Smuzhiyun #define CLK_TOP_UART0_SEL 128 161*4882a593Smuzhiyun #define CLK_TOP_EMI_DDRPHY_SEL 129 162*4882a593Smuzhiyun #define CLK_TOP_AHB_INFRA_SEL 130 163*4882a593Smuzhiyun #define CLK_TOP_MSDC0_SEL 131 164*4882a593Smuzhiyun #define CLK_TOP_UART1_SEL 132 165*4882a593Smuzhiyun #define CLK_TOP_MSDC1_SEL 133 166*4882a593Smuzhiyun #define CLK_TOP_PMICSPI_SEL 134 167*4882a593Smuzhiyun #define CLK_TOP_QAXI_AUD26M_SEL 135 168*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS_SEL 136 169*4882a593Smuzhiyun #define CLK_TOP_NFI2X_PAD_SEL 137 170*4882a593Smuzhiyun #define CLK_TOP_NFI1X_PAD_SEL 138 171*4882a593Smuzhiyun #define CLK_TOP_DDRPHYCFG_SEL 139 172*4882a593Smuzhiyun #define CLK_TOP_USB_78M_SEL 140 173*4882a593Smuzhiyun #define CLK_TOP_SPINOR_SEL 141 174*4882a593Smuzhiyun #define CLK_TOP_MSDC2_SEL 142 175*4882a593Smuzhiyun #define CLK_TOP_ETH_SEL 143 176*4882a593Smuzhiyun #define CLK_TOP_AUD1_SEL 144 177*4882a593Smuzhiyun #define CLK_TOP_AUD2_SEL 145 178*4882a593Smuzhiyun #define CLK_TOP_AUD_ENGEN1_SEL 146 179*4882a593Smuzhiyun #define CLK_TOP_AUD_ENGEN2_SEL 147 180*4882a593Smuzhiyun #define CLK_TOP_I2C_SEL 148 181*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S0_M_SEL 149 182*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S1_M_SEL 150 183*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S2_M_SEL 151 184*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S3_M_SEL 152 185*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S4_M_SEL 153 186*4882a593Smuzhiyun #define CLK_TOP_AUD_I2S5_M_SEL 154 187*4882a593Smuzhiyun #define CLK_TOP_AUD_SPDIF_B_SEL 155 188*4882a593Smuzhiyun #define CLK_TOP_PWM_SEL 156 189*4882a593Smuzhiyun #define CLK_TOP_SPI_SEL 157 190*4882a593Smuzhiyun #define CLK_TOP_AUD_SPDIFIN_SEL 158 191*4882a593Smuzhiyun #define CLK_TOP_UART2_SEL 159 192*4882a593Smuzhiyun #define CLK_TOP_BSI_SEL 160 193*4882a593Smuzhiyun #define CLK_TOP_DBG_ATCLK_SEL 161 194*4882a593Smuzhiyun #define CLK_TOP_CSW_NFIECC_SEL 162 195*4882a593Smuzhiyun #define CLK_TOP_NFIECC_SEL 163 196*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV0 164 197*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV1 165 198*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV2 166 199*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV3 167 200*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV4 168 201*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV4B 169 202*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV5 170 203*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV5B 171 204*4882a593Smuzhiyun #define CLK_TOP_APLL12_CK_DIV6 172 205*4882a593Smuzhiyun #define CLK_TOP_USB_78M 173 206*4882a593Smuzhiyun #define CLK_TOP_MSDC0_INFRA 174 207*4882a593Smuzhiyun #define CLK_TOP_MSDC1_INFRA 175 208*4882a593Smuzhiyun #define CLK_TOP_MSDC2_INFRA 176 209*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 177 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* AUDSYS */ 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #define CLK_AUD_AFE 0 214*4882a593Smuzhiyun #define CLK_AUD_I2S 1 215*4882a593Smuzhiyun #define CLK_AUD_22M 2 216*4882a593Smuzhiyun #define CLK_AUD_24M 3 217*4882a593Smuzhiyun #define CLK_AUD_INTDIR 4 218*4882a593Smuzhiyun #define CLK_AUD_APLL2_TUNER 5 219*4882a593Smuzhiyun #define CLK_AUD_APLL_TUNER 6 220*4882a593Smuzhiyun #define CLK_AUD_HDMI 7 221*4882a593Smuzhiyun #define CLK_AUD_SPDF 8 222*4882a593Smuzhiyun #define CLK_AUD_ADC 9 223*4882a593Smuzhiyun #define CLK_AUD_DAC 10 224*4882a593Smuzhiyun #define CLK_AUD_DAC_PREDIS 11 225*4882a593Smuzhiyun #define CLK_AUD_TML 12 226*4882a593Smuzhiyun #define CLK_AUD_NR_CLK 13 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT8516_H */ 229