| /OK3568_Linux_fs/u-boot/include/configs/ |
| H A D | MPC8610HPCD.h | 301 #define CONFIG_SYS_DBAT0L (BATL_PP_RW)
302 #define CONFIG_SYS_IBAT0L (BATL_PP_RW)
311 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
314 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
322 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
325 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
333 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
336 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
341 | BATL_PP_RW | BATL_CACHEINHIBIT \
346 | BATL_PP_RW | BATL_CACHEINHIBIT)
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| H A D | xpedite517x.h | 329 BATL_PP_RW |\
337 BATL_PP_RW |\
346 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
348 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
356 BATL_PP_RW |\
364 BATL_PP_RW |\
373 BATL_PP_RW |\
381 BATL_PP_RW |\
390 BATL_PP_RW |\
398 BATL_PP_RW |\
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| H A D | sbc8641d.h | 351 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
353 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
362 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
365 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
372 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
375 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
382 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
385 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
390 | BATL_PP_RW | BATL_CACHEINHIBIT \
395 | BATL_PP_RW | BATL_CACHEINHIBIT)
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| H A D | MPC8641HPCN.h | 437 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
438 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
445 | BATL_PP_RW | BATL_CACHEINHIBIT | \
451 | BATL_PP_RW | BATL_MEMCOHERENCE)
463 | BATL_PP_RW | BATL_CACHEINHIBIT \
469 | BATL_PP_RW | BATL_CACHEINHIBIT)
474 | BATL_PP_RW | BATL_CACHEINHIBIT | \
480 | BATL_PP_RW | BATL_CACHEINHIBIT)
489 | BATL_PP_RW | BATL_CACHEINHIBIT \
495 | BATL_PP_RW | BATL_CACHEINHIBIT)
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| H A D | TQM834x.h | 335 | BATL_PP_RW \
342 | BATL_PP_RW \
351 | BATL_PP_RW \
362 | BATL_PP_RW \
369 | BATL_PP_RW \
377 | BATL_PP_RW \
395 | BATL_PP_RW \
405 | BATL_PP_RW \
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| H A D | MPC837XERDB.h | 526 | BATL_PP_RW \
536 | BATL_PP_RW \
547 | BATL_PP_RW \
559 | BATL_PP_RW \
571 | BATL_PP_RW \
578 | BATL_PP_RW \
584 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
595 | BATL_PP_RW \
605 | BATL_PP_RW \
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| H A D | MPC837XEMDS.h | 511 | BATL_PP_RW \
521 | BATL_PP_RW \
532 | BATL_PP_RW \
544 | BATL_PP_RW \
556 | BATL_PP_RW \
563 | BATL_PP_RW \
569 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
580 | BATL_PP_RW \
590 | BATL_PP_RW \
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| H A D | MPC832XEMDS.h | 439 | BATL_PP_RW \
450 | BATL_PP_RW \
462 | BATL_PP_RW \
474 | BATL_PP_RW \
481 | BATL_PP_RW \
492 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
503 | BATL_PP_RW \
513 | BATL_PP_RW \
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| H A D | vme8349.h | 423 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
431 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
435 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
447 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
451 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
463 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
468 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
473 BATL_PP_RW | BATL_MEMCOHERENCE)
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| H A D | MPC8323ERDB.h | 354 | BATL_PP_RW \
365 | BATL_PP_RW \
377 | BATL_PP_RW \
384 | BATL_PP_RW \
395 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
406 | BATL_PP_RW \
416 | BATL_PP_RW \
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| H A D | sbc8349.h | 503 | BATL_PP_RW \
514 | BATL_PP_RW \
521 | BATL_PP_RW \
537 | BATL_PP_RW \
544 | BATL_PP_RW \
560 | BATL_PP_RW \
570 | BATL_PP_RW \
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| H A D | MPC8315ERDB.h | 480 | BATL_PP_RW \
491 | BATL_PP_RW \
503 | BATL_PP_RW \
510 | BATL_PP_RW \
516 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
526 | BATL_PP_RW \
537 | BATL_PP_RW \
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| H A D | MPC8349ITX.h | 568 | BATL_PP_RW \
578 | BATL_PP_RW \
585 | BATL_PP_RW \
601 | BATL_PP_RW \
608 | BATL_PP_RW \
624 | BATL_PP_RW \
634 | BATL_PP_RW \
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| H A D | ve8313.h | 383 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
391 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
397 | BATL_PP_RW \
419 | BATL_PP_RW \
428 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
432 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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| H A D | tuxx1.h | 161 BATL_PP_RW | \
169 BATL_PP_RW | \
181 BATL_PP_RW | \
188 BATL_PP_RW | \
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| H A D | suvd3.h | 140 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
144 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
155 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
159 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
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| H A D | MPC8349EMDS.h | 591 | BATL_PP_RW \
602 | BATL_PP_RW \
609 | BATL_PP_RW \
625 | BATL_PP_RW \
632 | BATL_PP_RW \
648 | BATL_PP_RW \
658 | BATL_PP_RW \
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| H A D | mpc8308_p1m.h | 420 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
428 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
436 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
440 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
446 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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| H A D | MPC8308RDB.h | 454 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
462 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
470 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
474 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
480 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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| H A D | hrcon.h | 548 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
556 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
564 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
568 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
574 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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| H A D | MPC8313ERDB.h | 557 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
564 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
570 | BATL_PP_RW \
586 | BATL_PP_RW \
595 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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| H A D | strider.h | 582 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
590 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
598 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
602 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
608 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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| /OK3568_Linux_fs/u-boot/include/configs/km/ |
| H A D | km83xx-common.h | 244 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
252 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
260 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
264 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
269 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
273 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
278 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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| /OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc86xx/ |
| H A D | mp.c | 112 bootpg | BATL_PP_RW | BATL_MEMCOHERENCE); in setup_mp()
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| /OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/ |
| H A D | mmu.h | 176 #define BATL_PP_RW BATL_PP_10 macro
|