1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008-2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/processor.h>
9*4882a593Smuzhiyun #include <asm/mmu.h>
10*4882a593Smuzhiyun #include <ioports.h>
11*4882a593Smuzhiyun #include <lmb.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/mp.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
cpu_reset(int nr)17*4882a593Smuzhiyun int cpu_reset(int nr)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun /* dummy function so common/cmd_mp.c will build
20*4882a593Smuzhiyun * should be implemented in the future, when cpu_release()
21*4882a593Smuzhiyun * is supported. Be aware there may be a similiar bug
22*4882a593Smuzhiyun * as exists on MPC85xx w/its PIC having a timing window
23*4882a593Smuzhiyun * associated to resetting the core */
24*4882a593Smuzhiyun return 1;
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
cpu_status(int nr)27*4882a593Smuzhiyun int cpu_status(int nr)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun /* dummy function so common/cmd_mp.c will build */
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
cpu_disable(int nr)33*4882a593Smuzhiyun int cpu_disable(int nr)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
36*4882a593Smuzhiyun volatile ccsr_gur_t *gur = &immap->im_gur;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun switch (nr) {
39*4882a593Smuzhiyun case 0:
40*4882a593Smuzhiyun setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
41*4882a593Smuzhiyun break;
42*4882a593Smuzhiyun case 1:
43*4882a593Smuzhiyun setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
44*4882a593Smuzhiyun break;
45*4882a593Smuzhiyun default:
46*4882a593Smuzhiyun printf("Invalid cpu number for disable %d\n", nr);
47*4882a593Smuzhiyun return 1;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
is_core_disabled(int nr)53*4882a593Smuzhiyun int is_core_disabled(int nr) {
54*4882a593Smuzhiyun immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
55*4882a593Smuzhiyun ccsr_gur_t *gur = &immap->im_gur;
56*4882a593Smuzhiyun u32 devdisr = in_be32(&gur->devdisr);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun switch (nr) {
59*4882a593Smuzhiyun case 0:
60*4882a593Smuzhiyun return (devdisr & MPC86xx_DEVDISR_CPU0);
61*4882a593Smuzhiyun case 1:
62*4882a593Smuzhiyun return (devdisr & MPC86xx_DEVDISR_CPU1);
63*4882a593Smuzhiyun default:
64*4882a593Smuzhiyun printf("Invalid cpu number for disable %d\n", nr);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
cpu_release(int nr,int argc,char * const argv[])70*4882a593Smuzhiyun int cpu_release(int nr, int argc, char * const argv[])
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun /* dummy function so common/cmd_mp.c will build
73*4882a593Smuzhiyun * should be implemented in the future */
74*4882a593Smuzhiyun return 1;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
determine_mp_bootpg(unsigned int * pagesize)77*4882a593Smuzhiyun u32 determine_mp_bootpg(unsigned int *pagesize)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun if (pagesize)
80*4882a593Smuzhiyun *pagesize = 4096;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
83*4882a593Smuzhiyun if ((u64)gd->ram_size > 0xfffff000)
84*4882a593Smuzhiyun return (0xfff00000);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return (gd->ram_size - (1024 * 1024));
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
cpu_mp_lmb_reserve(struct lmb * lmb)89*4882a593Smuzhiyun void cpu_mp_lmb_reserve(struct lmb *lmb)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun u32 bootpg = determine_mp_bootpg(NULL);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* tell u-boot we stole a page */
94*4882a593Smuzhiyun lmb_reserve(lmb, bootpg, 4096);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * Copy the code for other cpus to execute into an
99*4882a593Smuzhiyun * aligned location accessible via BPTR
100*4882a593Smuzhiyun */
setup_mp(void)101*4882a593Smuzhiyun void setup_mp(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun extern ulong __secondary_start_page;
104*4882a593Smuzhiyun ulong fixup = (ulong)&__secondary_start_page;
105*4882a593Smuzhiyun u32 bootpg = determine_mp_bootpg(NULL);
106*4882a593Smuzhiyun u32 bootpg_va;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
109*4882a593Smuzhiyun /* We're not covered by the DDR mapping, set up BAT */
110*4882a593Smuzhiyun write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
111*4882a593Smuzhiyun BATU_VS | BATU_VP,
112*4882a593Smuzhiyun bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
113*4882a593Smuzhiyun bootpg_va = CONFIG_SYS_SCRATCH_VA;
114*4882a593Smuzhiyun } else {
115*4882a593Smuzhiyun bootpg_va = bootpg;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun memcpy((void *)bootpg_va, (void *)fixup, 4096);
119*4882a593Smuzhiyun flush_cache(bootpg_va, 4096);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* remove the temporary BAT mapping */
122*4882a593Smuzhiyun if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
123*4882a593Smuzhiyun write_bat(DBAT7, 0, 0);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* If the physical location of bootpg is not at fff00000, set BPTR */
126*4882a593Smuzhiyun if (bootpg != 0xfff00000)
127*4882a593Smuzhiyun out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
128*4882a593Smuzhiyun (bootpg >> 12));
129*4882a593Smuzhiyun }
130