1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 /* 7 * mpc8313epb board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 17 #define CONFIG_MPC831x 1 18 #define CONFIG_MPC8313 1 19 #define CONFIG_MPC8313ERDB 1 20 21 #ifdef CONFIG_NAND 22 #define CONFIG_SPL_INIT_MINIMAL 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 26 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_NS16550_MIN_FUNCTIONS 29 #endif 30 31 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 33 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 34 #define CONFIG_SPL_PAD_TO 0x4000 35 36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 39 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 40 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 41 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 42 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 45 #endif 46 47 #endif /* CONFIG_NAND */ 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #define CONFIG_SYS_TEXT_BASE 0xFE000000 51 #endif 52 53 #ifndef CONFIG_SYS_MONITOR_BASE 54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 55 #endif 56 57 #define CONFIG_PCI_INDIRECT_BRIDGE 58 #define CONFIG_FSL_ELBC 1 59 60 #define CONFIG_MISC_INIT_R 61 62 /* 63 * On-board devices 64 * 65 * TSEC1 is VSC switch 66 * TSEC2 is SoC TSEC 67 */ 68 #define CONFIG_VSC7385_ENET 69 #define CONFIG_TSEC2 70 71 #ifdef CONFIG_SYS_66MHZ 72 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 73 #elif defined(CONFIG_SYS_33MHZ) 74 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 75 #else 76 #error Unknown oscillator frequency. 77 #endif 78 79 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 80 81 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 82 83 #define CONFIG_SYS_IMMR 0xE0000000 84 85 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 86 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 87 #endif 88 89 #define CONFIG_SYS_MEMTEST_START 0x00001000 90 #define CONFIG_SYS_MEMTEST_END 0x07f00000 91 92 /* Early revs of this board will lock up hard when attempting 93 * to access the PMC registers, unless a JTAG debugger is 94 * connected, or some resistor modifications are made. 95 */ 96 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 97 98 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 99 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 100 101 /* 102 * Device configurations 103 */ 104 105 /* Vitesse 7385 */ 106 107 #ifdef CONFIG_VSC7385_ENET 108 109 #define CONFIG_TSEC1 110 111 /* The flash address and size of the VSC7385 firmware image */ 112 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 113 #define CONFIG_VSC7385_IMAGE_SIZE 8192 114 115 #endif 116 117 /* 118 * DDR Setup 119 */ 120 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 122 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 123 124 /* 125 * Manually set up DDR parameters, as this board does not 126 * seem to have the SPD connected to I2C. 127 */ 128 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 129 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 130 | CSCONFIG_ODT_RD_NEVER \ 131 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 132 | CSCONFIG_ROW_BIT_13 \ 133 | CSCONFIG_COL_BIT_10) 134 /* 0x80010102 */ 135 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 137 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 138 | (0 << TIMING_CFG0_WRT_SHIFT) \ 139 | (0 << TIMING_CFG0_RRT_SHIFT) \ 140 | (0 << TIMING_CFG0_WWT_SHIFT) \ 141 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 142 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 143 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 144 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 145 /* 0x00220802 */ 146 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 147 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 148 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 149 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 150 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 151 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 152 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 153 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 154 /* 0x3835a322 */ 155 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 156 | (5 << TIMING_CFG2_CPO_SHIFT) \ 157 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 158 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 159 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 160 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 161 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 162 /* 0x129048c6 */ /* P9-45,may need tuning */ 163 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 164 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 165 /* 0x05100500 */ 166 #if defined(CONFIG_DDR_2T_TIMING) 167 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 168 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 169 | SDRAM_CFG_DBW_32 \ 170 | SDRAM_CFG_2T_EN) 171 /* 0x43088000 */ 172 #else 173 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 175 | SDRAM_CFG_DBW_32) 176 /* 0x43080000 */ 177 #endif 178 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 179 /* set burst length to 8 for 32-bit data path */ 180 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 181 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 182 /* 0x44480632 */ 183 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 184 185 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 186 /*0x02000000*/ 187 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 188 | DDRCDR_PZ_NOMZ \ 189 | DDRCDR_NZ_NOMZ \ 190 | DDRCDR_M_ODR) 191 192 /* 193 * FLASH on the Local Bus 194 */ 195 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 196 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 197 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 198 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 199 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 200 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 201 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 202 203 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 204 | BR_PS_16 /* 16 bit port */ \ 205 | BR_MS_GPCM /* MSEL = GPCM */ \ 206 | BR_V) /* valid */ 207 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 208 | OR_GPCM_XACS \ 209 | OR_GPCM_SCY_9 \ 210 | OR_GPCM_EHTR \ 211 | OR_GPCM_EAD) 212 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 213 /* window base at flash base */ 214 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 215 /* 16 MB window size */ 216 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 220 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 225 !defined(CONFIG_SPL_BUILD) 226 #define CONFIG_SYS_RAMBOOT 227 #endif 228 229 #define CONFIG_SYS_INIT_RAM_LOCK 1 230 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 231 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 232 233 #define CONFIG_SYS_GBL_DATA_OFFSET \ 234 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 236 237 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 238 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 239 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 240 241 /* 242 * Local Bus LCRR and LBCR regs 243 */ 244 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 245 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 246 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 247 | (0xFF << LBCR_BMT_SHIFT) \ 248 | 0xF) /* 0x0004ff0f */ 249 250 /* LB refresh timer prescal, 266MHz/32 */ 251 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 252 253 /* drivers/mtd/nand/raw/nand.c */ 254 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 255 #define CONFIG_SYS_NAND_BASE 0xFFF00000 256 #else 257 #define CONFIG_SYS_NAND_BASE 0xE2800000 258 #endif 259 260 #define CONFIG_MTD_PARTITION 261 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 262 #define MTDPARTS_DEFAULT \ 263 "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" 264 265 #define CONFIG_SYS_MAX_NAND_DEVICE 1 266 #define CONFIG_NAND_FSL_ELBC 1 267 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 268 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 269 270 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 271 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 272 | BR_PS_8 /* 8 bit port */ \ 273 | BR_MS_FCM /* MSEL = FCM */ \ 274 | BR_V) /* valid */ 275 #define CONFIG_SYS_NAND_OR_PRELIM \ 276 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 277 | OR_FCM_CSCT \ 278 | OR_FCM_CST \ 279 | OR_FCM_CHT \ 280 | OR_FCM_SCY_1 \ 281 | OR_FCM_TRLX \ 282 | OR_FCM_EHTR) 283 /* 0xFFFF8396 */ 284 285 #ifdef CONFIG_NAND 286 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 287 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 288 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 289 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 290 #else 291 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 292 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 293 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 294 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 295 #endif 296 297 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 298 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 299 300 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 301 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 302 303 /* local bus write LED / read status buffer (BCSR) mapping */ 304 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 305 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 306 /* map at 0xFA000000 on LCS3 */ 307 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 308 | BR_PS_8 /* 8 bit port */ \ 309 | BR_MS_GPCM /* MSEL = GPCM */ \ 310 | BR_V) /* valid */ 311 /* 0xFA000801 */ 312 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 313 | OR_GPCM_CSNT \ 314 | OR_GPCM_ACS_DIV2 \ 315 | OR_GPCM_XACS \ 316 | OR_GPCM_SCY_15 \ 317 | OR_GPCM_TRLX_SET \ 318 | OR_GPCM_EHTR_SET \ 319 | OR_GPCM_EAD) 320 /* 0xFFFF8FF7 */ 321 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 322 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 323 324 /* Vitesse 7385 */ 325 326 #ifdef CONFIG_VSC7385_ENET 327 328 /* VSC7385 Base address on LCS2 */ 329 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 330 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 331 332 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 333 | BR_PS_8 /* 8 bit port */ \ 334 | BR_MS_GPCM /* MSEL = GPCM */ \ 335 | BR_V) /* valid */ 336 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 337 | OR_GPCM_CSNT \ 338 | OR_GPCM_XACS \ 339 | OR_GPCM_SCY_15 \ 340 | OR_GPCM_SETA \ 341 | OR_GPCM_TRLX_SET \ 342 | OR_GPCM_EHTR_SET \ 343 | OR_GPCM_EAD) 344 /* 0xFFFE09FF */ 345 346 /* Access window base at VSC7385 base */ 347 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 348 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 349 350 #endif 351 352 #define CONFIG_MPC83XX_GPIO 1 353 354 /* 355 * Serial Port 356 */ 357 #define CONFIG_CONS_INDEX 1 358 #define CONFIG_SYS_NS16550_SERIAL 359 #define CONFIG_SYS_NS16550_REG_SIZE 1 360 361 #define CONFIG_SYS_BAUDRATE_TABLE \ 362 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 363 364 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 365 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 366 367 /* I2C */ 368 #define CONFIG_SYS_I2C 369 #define CONFIG_SYS_I2C_FSL 370 #define CONFIG_SYS_FSL_I2C_SPEED 400000 371 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 372 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 373 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 374 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 375 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 376 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 377 378 /* 379 * General PCI 380 * Addresses are mapped 1-1. 381 */ 382 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 383 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 384 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 385 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 386 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 387 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 388 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 389 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 390 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 391 392 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 393 394 /* 395 * TSEC 396 */ 397 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 398 399 #define CONFIG_GMII /* MII PHY management */ 400 401 #ifdef CONFIG_TSEC1 402 #define CONFIG_HAS_ETH0 403 #define CONFIG_TSEC1_NAME "TSEC0" 404 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 405 #define TSEC1_PHY_ADDR 0x1c 406 #define TSEC1_FLAGS TSEC_GIGABIT 407 #define TSEC1_PHYIDX 0 408 #endif 409 410 #ifdef CONFIG_TSEC2 411 #define CONFIG_HAS_ETH1 412 #define CONFIG_TSEC2_NAME "TSEC1" 413 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 414 #define TSEC2_PHY_ADDR 4 415 #define TSEC2_FLAGS TSEC_GIGABIT 416 #define TSEC2_PHYIDX 0 417 #endif 418 419 /* Options are: TSEC[0-1] */ 420 #define CONFIG_ETHPRIME "TSEC1" 421 422 /* 423 * Configure on-board RTC 424 */ 425 #define CONFIG_RTC_DS1337 426 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 427 428 /* 429 * Environment 430 */ 431 #if defined(CONFIG_NAND) 432 #define CONFIG_ENV_OFFSET (512 * 1024) 433 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 434 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 435 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 436 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 437 #define CONFIG_ENV_OFFSET_REDUND \ 438 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 439 #elif !defined(CONFIG_SYS_RAMBOOT) 440 #define CONFIG_ENV_ADDR \ 441 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 442 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 443 #define CONFIG_ENV_SIZE 0x2000 444 445 /* Address and size of Redundant Environment Sector */ 446 #else 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 448 #define CONFIG_ENV_SIZE 0x2000 449 #endif 450 451 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 452 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 453 454 /* 455 * BOOTP options 456 */ 457 #define CONFIG_BOOTP_BOOTFILESIZE 458 #define CONFIG_BOOTP_BOOTPATH 459 #define CONFIG_BOOTP_GATEWAY 460 #define CONFIG_BOOTP_HOSTNAME 461 462 /* 463 * Command line configuration. 464 */ 465 466 #define CONFIG_CMDLINE_EDITING 1 467 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 468 469 /* 470 * Miscellaneous configurable options 471 */ 472 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 473 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 474 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 475 476 /* Boot Argument Buffer Size */ 477 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 478 479 /* 480 * For booting Linux, the board info and command line data 481 * have to be in the first 256 MB of memory, since this is 482 * the maximum mapped by the Linux kernel during initialization. 483 */ 484 /* Initial Memory map for Linux*/ 485 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 486 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 487 488 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 489 490 #ifdef CONFIG_SYS_66MHZ 491 492 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 493 /* 0x62040000 */ 494 #define CONFIG_SYS_HRCW_LOW (\ 495 0x20000000 /* reserved, must be set */ |\ 496 HRCWL_DDRCM |\ 497 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 498 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 499 HRCWL_CSB_TO_CLKIN_2X1 |\ 500 HRCWL_CORE_TO_CSB_2X1) 501 502 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 503 504 #elif defined(CONFIG_SYS_33MHZ) 505 506 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 507 /* 0x65040000 */ 508 #define CONFIG_SYS_HRCW_LOW (\ 509 0x20000000 /* reserved, must be set */ |\ 510 HRCWL_DDRCM |\ 511 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 512 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 513 HRCWL_CSB_TO_CLKIN_5X1 |\ 514 HRCWL_CORE_TO_CSB_2X1) 515 516 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 517 518 #endif 519 520 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 521 HRCWH_PCI_HOST |\ 522 HRCWH_PCI1_ARBITER_ENABLE |\ 523 HRCWH_CORE_ENABLE |\ 524 HRCWH_BOOTSEQ_DISABLE |\ 525 HRCWH_SW_WATCHDOG_DISABLE |\ 526 HRCWH_TSEC1M_IN_RGMII |\ 527 HRCWH_TSEC2M_IN_RGMII |\ 528 HRCWH_BIG_ENDIAN) 529 530 #ifdef CONFIG_NAND 531 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 532 HRCWH_FROM_0XFFF00100 |\ 533 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 534 HRCWH_RL_EXT_NAND) 535 #else 536 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 537 HRCWH_FROM_0X00000100 |\ 538 HRCWH_ROM_LOC_LOCAL_16BIT |\ 539 HRCWH_RL_EXT_LEGACY) 540 #endif 541 542 /* System IO Config */ 543 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 544 /* Enable Internal USB Phy and GPIO on LCD Connector */ 545 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 546 547 #define CONFIG_SYS_HID0_INIT 0x000000000 548 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 549 HID0_ENABLE_INSTRUCTION_CACHE | \ 550 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 551 552 #define CONFIG_SYS_HID2 HID2_HBE 553 554 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 555 556 /* DDR @ 0x00000000 */ 557 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 558 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 559 | BATU_BL_256M \ 560 | BATU_VS \ 561 | BATU_VP) 562 563 /* PCI @ 0x80000000 */ 564 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 565 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 566 | BATU_BL_256M \ 567 | BATU_VS \ 568 | BATU_VP) 569 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 570 | BATL_PP_RW \ 571 | BATL_CACHEINHIBIT \ 572 | BATL_GUARDEDSTORAGE) 573 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 574 | BATU_BL_256M \ 575 | BATU_VS \ 576 | BATU_VP) 577 578 /* PCI2 not supported on 8313 */ 579 #define CONFIG_SYS_IBAT3L (0) 580 #define CONFIG_SYS_IBAT3U (0) 581 #define CONFIG_SYS_IBAT4L (0) 582 #define CONFIG_SYS_IBAT4U (0) 583 584 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 585 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 586 | BATL_PP_RW \ 587 | BATL_CACHEINHIBIT \ 588 | BATL_GUARDEDSTORAGE) 589 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 590 | BATU_BL_256M \ 591 | BATU_VS \ 592 | BATU_VP) 593 594 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 595 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 596 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 597 598 #define CONFIG_SYS_IBAT7L (0) 599 #define CONFIG_SYS_IBAT7U (0) 600 601 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 602 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 603 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 604 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 605 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 606 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 607 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 608 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 609 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 610 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 611 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 612 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 613 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 614 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 615 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 616 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 617 618 /* 619 * Environment Configuration 620 */ 621 #define CONFIG_ENV_OVERWRITE 622 623 #define CONFIG_NETDEV "eth1" 624 625 #define CONFIG_HOSTNAME mpc8313erdb 626 #define CONFIG_ROOTPATH "/nfs/root/path" 627 #define CONFIG_BOOTFILE "uImage" 628 /* U-Boot image on TFTP server */ 629 #define CONFIG_UBOOTPATH "u-boot.bin" 630 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 631 632 /* default location for tftp and bootm */ 633 #define CONFIG_LOADADDR 800000 634 635 #define CONFIG_EXTRA_ENV_SETTINGS \ 636 "netdev=" CONFIG_NETDEV "\0" \ 637 "ethprime=TSEC1\0" \ 638 "uboot=" CONFIG_UBOOTPATH "\0" \ 639 "tftpflash=tftpboot $loadaddr $uboot; " \ 640 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 641 " +$filesize; " \ 642 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 643 " +$filesize; " \ 644 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 645 " $filesize; " \ 646 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 647 " +$filesize; " \ 648 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 649 " $filesize\0" \ 650 "fdtaddr=780000\0" \ 651 "fdtfile=" CONFIG_FDTFILE "\0" \ 652 "console=ttyS0\0" \ 653 "setbootargs=setenv bootargs " \ 654 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 655 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 656 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 657 "$netdev:off " \ 658 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 659 660 #define CONFIG_NFSBOOTCOMMAND \ 661 "setenv rootdev /dev/nfs;" \ 662 "run setbootargs;" \ 663 "run setipargs;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr - $fdtaddr" 667 668 #define CONFIG_RAMBOOTCOMMAND \ 669 "setenv rootdev /dev/ram;" \ 670 "run setbootargs;" \ 671 "tftp $ramdiskaddr $ramdiskfile;" \ 672 "tftp $loadaddr $bootfile;" \ 673 "tftp $fdtaddr $fdtfile;" \ 674 "bootm $loadaddr $ramdiskaddr $fdtaddr" 675 676 #endif /* __CONFIG_H */ 677