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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SPI Controller
10 The Rockchip SPI controller is used to interface with various devices such
11 as flash and display controllers using the SPI communication interface.
14 - $ref: "spi-controller.yaml#"
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rk3036-spi
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3xxx.dtsi5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
39 dmac1_s: dma-controller@20018000 {
44 #dma-cells = <1>;
45 arm,pl330-broken-no-flushp;
[all …]
H A D.rk3188-radxarock.dtb.dts.tmp
H A Drk3188.dtsi5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3188-cru.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points = <
[all …]
H A D.rk3066a-mk808.dtb.dts.tmp
H A Drk3308.dtsi4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rk3308-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
34 #address-cells = <2>;
[all …]
H A D.rk3308-evb.dtb.dts.tmp
H A Drk3288.dtsi2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
18 interrupt-parent = <&gic>;
[all …]
H A Drk3399.dtsi2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3399-power.h>
13 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
[all …]
H A D.rk3288-vyasa.dtb.dts.tmp
H A D.rk3288-rock2-square.dtb.dts.tmp
H A D.rk3288-popmetal.dtb.dts.tmp
H A D.rk3288-tinker.dtb.dts.tmp
H A D.rk3288-evb.dtb.dts.tmp
H A D.rk3288-fennec.dtb.dts.tmp
H A D.rk3288-firefly.dtb.dts.tmp
H A D.rk3288-miqi.dtb.dts.tmp
H A D.rk3288-phycore-rdk.dtb.dts.tmp
H A Drk3368.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/memory/rk3368-dmc.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "rockchip,rk3066-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/power/rk3036-power.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/suspend/rockchip-rk3288.h>
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A DKconfig18 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
19 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
26 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
55 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
58 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
66 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
67 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
[all …]

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