1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3036-cru.h> 8#include <dt-bindings/power/rk3036-power.h> 9#include <dt-bindings/soc/rockchip,boot-mode.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 compatible = "rockchip,rk3036"; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 ethernet0 = &emac; 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 mshc0 = &emmc; 28 mshc1 = &sdmmc; 29 mshc2 = &sdio; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &uart2; 33 spi = &spi; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 enable-method = "rockchip,rk3036-smp"; 40 41 cpu0: cpu@f00 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a7"; 44 reg = <0xf00>; 45 resets = <&cru SRST_CORE0>; 46 operating-points-v2 = <&cpu0_opp_table>; 47 clocks = <&cru ARMCLK>; 48 }; 49 50 cpu1: cpu@f01 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a7"; 53 reg = <0xf01>; 54 resets = <&cru SRST_CORE1>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 }; 57 }; 58 59 cpu0_opp_table: opp_table0 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-408000000 { 64 opp-hz = /bits/ 64 <408000000>; 65 opp-microvolt = <1000000 1000000 1225000>; 66 clock-latency-ns = <40000>; 67 }; 68 opp-600000000 { 69 opp-hz = /bits/ 64 <600000000>; 70 opp-microvolt = <1000000 1000000 1225000>; 71 clock-latency-ns = <40000>; 72 }; 73 opp-816000000 { 74 opp-hz = /bits/ 64 <816000000>; 75 opp-microvolt = <1100000 1100000 1225000>; 76 clock-latency-ns = <40000>; 77 opp-suspend; 78 }; 79 opp-1008000000 { 80 opp-hz = /bits/ 64 <1008000000>; 81 opp-microvolt = <1150000 1150000 1225000>; 82 clock-latency-ns = <40000>; 83 }; 84 opp-1200000000 { 85 opp-hz = /bits/ 64 <1200000000>; 86 opp-microvolt = <1225000 1225000 1225000>; 87 clock-latency-ns = <40000>; 88 }; 89 }; 90 91 amba: bus { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges; 96 97 pdma: pdma@20078000 { 98 compatible = "arm,pl330", "arm,primecell"; 99 reg = <0x20078000 0x4000>; 100 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 102 #dma-cells = <1>; 103 arm,pl330-broken-no-flushp; 104 arm,pl330-periph-burst; 105 clocks = <&cru ACLK_DMAC2>; 106 clock-names = "apb_pclk"; 107 }; 108 }; 109 110 arm-pmu { 111 compatible = "arm,cortex-a7-pmu"; 112 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&cpu0>, <&cpu1>; 115 }; 116 117 display-subsystem { 118 compatible = "rockchip,display-subsystem"; 119 ports = <&vop_out>; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0"; 124 method = "smc"; 125 }; 126 127 timer { 128 compatible = "arm,armv7-timer"; 129 arm,cpu-registers-not-fw-configured; 130 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 131 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 132 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 133 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 134 clock-frequency = <24000000>; 135 }; 136 137 xin24m: oscillator { 138 compatible = "fixed-clock"; 139 clock-frequency = <24000000>; 140 clock-output-names = "xin24m"; 141 #clock-cells = <0>; 142 }; 143 144 bus_intmem: sram@10080000 { 145 compatible = "mmio-sram"; 146 reg = <0x10080000 0x2000>; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 ranges = <0 0x10080000 0x2000>; 150 151 smp-sram@0 { 152 compatible = "rockchip,rk3066-smp-sram"; 153 reg = <0x00 0x10>; 154 }; 155 }; 156 157 gpu: gpu@10090000 { 158 compatible = "arm,mali400"; 159 reg = <0x10090000 0x10000>; 160 upthreshold = <40>; 161 downdifferential = <10>; 162 163 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 167 168 interrupt-names = "Mali_GP_IRQ", 169 "Mali_GP_MMU_IRQ", 170 "Mali_PP0_IRQ", 171 "Mali_PP0_MMU_IRQ"; 172 173 clocks = <&cru SCLK_GPU>; 174 clock-names = "clk_mali"; 175 assigned-clocks = <&cru SCLK_GPU>; 176 assigned-clock-rates = <400000000>; 177 assigned-clock-parents = <&cru PLL_DPLL>; 178 power-domains = <&power RK3036_PD_GPU>; 179 operating-points-v2 = <&gpu_opp_table>; 180 181 status = "disabled"; 182 183 gpu_power_model: power_model { 184 compatible = "arm,mali-simple-power-model"; 185 voltage = <900>; 186 frequency = <500>; 187 static-power = <300>; 188 dynamic-power = <396>; 189 ts = <32000 4700 (-80) 2>; 190 thermal-zone = "soc-thermal"; 191 }; 192 }; 193 194 gpu_opp_table: opp-table1 { 195 compatible = "operating-points-v2"; 196 197 opp-200000000 { 198 opp-hz = /bits/ 64 <200000000>; 199 opp-microvolt = <1000000>; 200 }; 201 opp-400000000 { 202 opp-hz = /bits/ 64 <400000000>; 203 opp-microvolt = <1100000>; 204 }; 205 }; 206 207 mpp_srv: mpp-srv { 208 compatible = "rockchip,mpp-service"; 209 rockchip,taskqueue-count = <1>; 210 rockchip,resetgroup-count = <1>; 211 rockchip,grf = <&grf>; 212 rockchip,grf-offset = <0x0144>; 213 rockchip,grf-values = <0x0008000a>, <0x00080002>; 214 rockchip,grf-names = "grf_rkvdec", "grf_vdpu1"; 215 status = "disabled"; 216 }; 217 218 vdpu: vdpu@10108400 { 219 compatible = "rockchip,vpu-decoder-rk3036"; 220 reg = <0x10108400 0x400>; 221 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 222 interrupt-names = "irq_dec"; 223 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 224 clock-names = "aclk_vcodec", "hclk_vcodec"; 225 rockchip,normal-rates = <297000000>, <0>; 226 assigned-clocks = <&cru ACLK_VCODEC>; 227 assigned-clock-rates = <297000000>; 228 assigned-clock-parents = <&cru PLL_GPLL>; 229 resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>; 230 reset-names = "shared_video_a", "shared_video_h"; 231 iommus = <&vpu_mmu>; 232 power-domains = <&power RK3036_PD_VPU>; 233 rockchip,srv = <&mpp_srv>; 234 rockchip,taskqueue-node = <0>; 235 rockchip,resetgroup-node = <0>; 236 status = "disabled"; 237 }; 238 239 vpu_mmu: iommu@10108800 { 240 compatible = "rockchip,iommu"; 241 reg = <0x10108800 0x100>; 242 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-names = "vpu_mmu"; 244 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 245 clock-names = "aclk", "iface"; 246 #iommu-cells = <0>; 247 power-domains = <&power RK3036_PD_VPU>; 248 status = "disabled"; 249 }; 250 251 hevc: hevc_service@1010c000 { 252 compatible = "rockchip,hevc-decoder-rk3036"; 253 reg = <0x1010c000 0x400>; 254 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-names = "irq_dec"; 256 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>, <&cru ACLK_HEVC>; 257 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 258 rockchip,normal-rates = <297000000>, <0>, <200000000>; 259 assigned-clocks = <&cru ACLK_VCODEC>; 260 assigned-clock-rates = <297000000>; 261 assigned-clock-parents = <&cru PLL_GPLL>; 262 resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>, <&cru SRST_HEVC>; 263 reset-names = "shared_video_a", "shared_video_h", "video_core"; 264 iommus = <&hevc_mmu>; 265 rockchip,srv = <&mpp_srv>; 266 rockchip,taskqueue-node = <0>; 267 rockchip,resetgroup-node = <0>; 268 power-domains = <&power RK3036_PD_VPU>; 269 status = "disabled"; 270 }; 271 272 hevc_mmu: iommu@1010c440 { 273 compatible = "rockchip,iommu"; 274 reg = <0x1010c440 0x40>, <0x1010c480 0x40>; 275 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "hevc_mmu"; 277 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 278 clock-names = "aclk", "iface"; 279 #iommu-cells = <0>; 280 power-domains = <&power RK3036_PD_VPU>; 281 status = "disabled"; 282 }; 283 284 vop: vop@10118000 { 285 compatible = "rockchip,rk3036-vop"; 286 reg = <0x10118000 0x19c>; 287 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; 289 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 290 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; 291 reset-names = "axi", "ahb", "dclk"; 292 iommus = <&vop_mmu>; 293 status = "disabled"; 294 295 vop_out: port { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 vop_out_hdmi: endpoint@0 { 299 reg = <0>; 300 remote-endpoint = <&hdmi_in_vop>; 301 }; 302 vop_out_tve: endpoint@1 { 303 reg = <1>; 304 remote-endpoint = <&tve_in_vop>; 305 }; 306 }; 307 }; 308 309 tve: tve@10118200 { 310 compatible = "rockchip,rk3036-tve"; 311 reg = <0x10118200 0x100>; 312 clocks = <&cru ACLK_VIO>; 313 clock-names = "aclk"; 314 rockchip,saturation = <0x00386346>; 315 rockchip,brightcontrast = <0x00008b00>; 316 rockchip,adjtiming = <0xa6c00880>; 317 rockchip,lumafilter0 = <0x02ff0000>; 318 rockchip,lumafilter1 = <0xf40202fd>; 319 rockchip,lumafilter2 = <0xf332d919>; 320 rockchip,daclevel = <0x3e>; 321 rockchip,grf = <&grf>; 322 status = "disabled"; 323 324 ports { 325 tve_in: port { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 tve_in_vop: endpoint@0 { 329 reg = <0>; 330 remote-endpoint = <&vop_out_tve>; 331 }; 332 }; 333 }; 334 }; 335 336 vop_mmu: iommu@10118300 { 337 compatible = "rockchip,iommu"; 338 reg = <0x10118300 0x100>; 339 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "vop_mmu"; 341 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; 342 clock-names = "aclk", "iface"; 343 #iommu-cells = <0>; 344 status = "disabled"; 345 }; 346 347 qos_vpu: qos@1012e000 { 348 compatible = "syscon"; 349 reg = <0x0 0x1012e000 0x0 0x20>; 350 }; 351 352 gic: interrupt-controller@10139000 { 353 compatible = "arm,gic-400"; 354 interrupt-controller; 355 #interrupt-cells = <3>; 356 #address-cells = <0>; 357 358 reg = <0x10139000 0x1000>, 359 <0x1013a000 0x2000>, 360 <0x1013c000 0x2000>, 361 <0x1013e000 0x2000>; 362 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 363 }; 364 365 usb_otg: usb@10180000 { 366 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 367 "snps,dwc2"; 368 reg = <0x10180000 0x40000>; 369 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cru HCLK_OTG0>; 371 clock-names = "otg"; 372 dr_mode = "otg"; 373 g-np-tx-fifo-size = <16>; 374 g-rx-fifo-size = <280>; 375 g-tx-fifo-size = <256 128 128 64 32 16>; 376 status = "disabled"; 377 }; 378 379 usb_host: usb@101c0000 { 380 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 381 "snps,dwc2"; 382 reg = <0x101c0000 0x40000>; 383 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&cru HCLK_OTG1>; 385 clock-names = "otg"; 386 dr_mode = "host"; 387 status = "disabled"; 388 }; 389 390 emac: ethernet@10200000 { 391 compatible = "rockchip,rk3036-emac", "snps,arc-emac"; 392 reg = <0x10200000 0x4000>; 393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 rockchip,grf = <&grf>; 397 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; 398 clock-names = "hclk", "macref", "macclk"; 399 /* 400 * Fix the emac parent clock is DPLL instead of APLL. 401 * since that will cause some unstable things if the cpufreq 402 * is working. (e.g: the accurate 50MHz what mac_ref need) 403 */ 404 assigned-clocks = <&cru SCLK_MACPLL>; 405 assigned-clock-parents = <&cru PLL_DPLL>; 406 max-speed = <100>; 407 phy-mode = "rmii"; 408 status = "disabled"; 409 }; 410 411 spdif_tx: spdif-tx@10204000 { 412 compatible = "rockchip,rk3066-spdif"; 413 reg = <0x10204000 0x1000>; 414 clocks = <&cru SCLK_SPDIF>, <&cru SCLK_SPDIF>; 415 clock-names = "mclk", "hclk"; 416 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 417 dmas = <&pdma 13>; 418 dma-names = "tx"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&spdif_out>; 421 #sound-dai-cells = <0>; 422 status = "disabled"; 423 }; 424 425 sfc: sfc@10208000 { 426 compatible = "rockchip,sfc"; 427 reg = <0x10208000 0x200>; 428 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 430 clock-names = "clk_sfc", "hclk_sfc"; 431 status = "disabled"; 432 }; 433 434 sdmmc: dwmmc@10214000 { 435 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 436 reg = <0x10214000 0x4000>; 437 clock-frequency = <37500000>; 438 max-frequency = <37500000>; 439 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 440 clock-names = "biu", "ciu"; 441 fifo-depth = <0x100>; 442 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 443 resets = <&cru SRST_MMC0>; 444 reset-names = "reset"; 445 no-mmc; 446 no-sdio; 447 status = "disabled"; 448 }; 449 450 sdio: mmc@10218000 { 451 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 452 reg = <0x10218000 0x4000>; 453 max-frequency = <37500000>; 454 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 455 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 456 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 457 fifo-depth = <0x100>; 458 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 459 resets = <&cru SRST_SDIO>; 460 reset-names = "reset"; 461 no-mmc; 462 no-sd; 463 status = "disabled"; 464 }; 465 466 emmc: mmc@1021c000 { 467 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 468 reg = <0x1021c000 0x4000>; 469 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 470 bus-width = <8>; 471 cap-mmc-highspeed; 472 clock-frequency = <37500000>; 473 max-frequency = <37500000>; 474 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 475 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 476 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 477 rockchip,default-sample-phase = <158>; 478 disable-wp; 479 dmas = <&pdma 12>; 480 dma-names = "rx-tx"; 481 fifo-depth = <0x100>; 482 non-removable; 483 no-sdio; 484 no-sd; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 487 resets = <&cru SRST_EMMC>; 488 reset-names = "reset"; 489 status = "disabled"; 490 }; 491 492 i2s: i2s@10220000 { 493 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; 494 reg = <0x10220000 0x4000>; 495 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 496 clock-names = "i2s_clk", "i2s_hclk"; 497 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; 498 assigned-clocks = <&cru SCLK_I2S_PRE>; 499 assigned-clock-parents = <&cru SCLK_I2S_FRAC>; 500 dmas = <&pdma 0>, <&pdma 1>; 501 dma-names = "tx", "rx"; 502 resets = <&cru SRST_I2S>; 503 reset-names = "reset-m"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&i2s_mclk 506 &i2s_sclk 507 &i2s_lrclkrx 508 &i2s_lrclktx 509 &i2s_sdo 510 &i2s_sdi>; 511 #sound-dai-cells = <0>; 512 status = "disabled"; 513 }; 514 515 cru: clock-controller@20000000 { 516 compatible = "rockchip,rk3036-cru"; 517 reg = <0x20000000 0x1000>; 518 rockchip,grf = <&grf>; 519 #clock-cells = <1>; 520 #reset-cells = <1>; 521 assigned-clocks = <&cru PLL_GPLL>; 522 assigned-clock-rates = <594000000>; 523 }; 524 525 grf: syscon@20008000 { 526 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; 527 reg = <0x20008000 0x1000>; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 531 reboot-mode { 532 compatible = "syscon-reboot-mode"; 533 offset = <0x1d8>; 534 mode-normal = <BOOT_NORMAL>; 535 mode-recovery = <BOOT_RECOVERY>; 536 mode-bootloader = <BOOT_FASTBOOT>; 537 mode-loader = <BOOT_BL_DOWNLOAD>; 538 mode-ums = <BOOT_UMS>; 539 }; 540 541 power: power-controller { 542 compatible = "rockchip,rk3036-power-controller"; 543 #power-domain-cells = <1>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 547 pd_vpu@RK3036_PD_VPU { 548 reg = <RK3036_PD_VPU>; 549 clocks = <&cru ACLK_VCODEC>, 550 <&cru HCLK_VCODEC>, 551 <&cru ACLK_HEVC>; 552 pm_qos = <&qos_vpu>; 553 }; 554 pd_gpu@RK3036_PD_GPU { 555 reg = <RK3036_PD_GPU>; 556 clocks = <&cru SCLK_GPU>; 557 }; 558 }; 559 560 usb2phy: usb2-phy@17c { 561 compatible = "rockchip,rk3036-usb2phy"; 562 reg = <0x017c 0x0c>; 563 clocks = <&cru SCLK_OTGPHY0>; 564 clock-names = "phyclk"; 565 #clock-cells = <0>; 566 clock-output-names = "usb480m_phy"; 567 status = "disabled"; 568 569 u2phy_otg: otg-port { 570 #phy-cells = <0>; 571 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "otg-bvalid", "otg-id", 575 "linestate"; 576 status = "disabled"; 577 }; 578 579 u2phy_host: host-port { 580 #phy-cells = <0>; 581 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 582 interrupt-names = "linestate"; 583 status = "disabled"; 584 }; 585 }; 586 }; 587 588 acodec: acodec-ana@20030000 { 589 compatible = "rockchip,rk3036-codec"; 590 reg = <0x20030000 0x4000>; 591 rockchip,grf = <&grf>; 592 clock-names = "acodec_pclk"; 593 clocks = <&cru PCLK_ACODEC>; 594 status = "disabled"; 595 }; 596 597 hdmi: hdmi@20034000 { 598 compatible = "rockchip,rk3036-inno-hdmi"; 599 reg = <0x20034000 0x4000>; 600 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cru ACLK_VIO>, <&cru PCLK_HDMI>; 602 clock-names = "aclk", "pclk"; 603 rockchip,grf = <&grf>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&hdmi_ctl>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 #sound-dai-cells = <0>; 609 status = "disabled"; 610 611 hdmi_in: port { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 hdmi_in_vop: endpoint@0 { 615 reg = <0>; 616 remote-endpoint = <&vop_out_hdmi>; 617 }; 618 }; 619 }; 620 621 timer: timer@20044000 { 622 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; 623 reg = <0x20044000 0x20>; 624 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&xin24m>, <&cru PCLK_TIMER>; 626 clock-names = "timer", "pclk"; 627 }; 628 629 wdt: watchdog@2004c000 { 630 compatible = "rockchip,rk3036-wdt", "snps,dw-wdt"; 631 reg = <0x2004c000 0x100>; 632 clocks = <&cru PCLK_WDT>; 633 status = "disabled"; 634 }; 635 636 pwm0: pwm@20050000 { 637 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm"; 638 reg = <0x20050000 0x10>; 639 #pwm-cells = <3>; 640 clocks = <&cru PCLK_PWM>; 641 clock-names = "pwm"; 642 pinctrl-names = "active"; 643 pinctrl-0 = <&pwm0_pin>; 644 status = "disabled"; 645 }; 646 647 pwm1: pwm@20050010 { 648 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm"; 649 reg = <0x20050010 0x10>; 650 #pwm-cells = <3>; 651 clocks = <&cru PCLK_PWM>; 652 clock-names = "pwm"; 653 pinctrl-names = "active"; 654 pinctrl-0 = <&pwm1_pin>; 655 status = "disabled"; 656 }; 657 658 pwm2: pwm@20050020 { 659 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm"; 660 reg = <0x20050020 0x10>; 661 #pwm-cells = <3>; 662 clocks = <&cru PCLK_PWM>; 663 clock-names = "pwm"; 664 pinctrl-names = "active"; 665 pinctrl-0 = <&pwm2_pin>; 666 status = "disabled"; 667 }; 668 669 pwm3: pwm@20050030 { 670 compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm"; 671 reg = <0x20050030 0x10>; 672 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 673 #pwm-cells = <3>; 674 clocks = <&cru PCLK_PWM>; 675 clock-names = "pwm"; 676 pinctrl-names = "active"; 677 pinctrl-0 = <&pwm3_pin>; 678 status = "disabled"; 679 }; 680 681 i2c1: i2c@20056000 { 682 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 683 reg = <0x20056000 0x1000>; 684 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clock-names = "i2c"; 688 clocks = <&cru PCLK_I2C1>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&i2c1_xfer>; 691 status = "disabled"; 692 }; 693 694 i2c2: i2c@2005a000 { 695 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 696 reg = <0x2005a000 0x1000>; 697 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 clock-names = "i2c"; 701 clocks = <&cru PCLK_I2C2>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&i2c2_xfer>; 704 status = "disabled"; 705 }; 706 707 uart0: serial@20060000 { 708 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 709 reg = <0x20060000 0x100>; 710 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 711 reg-shift = <2>; 712 reg-io-width = <4>; 713 clock-frequency = <24000000>; 714 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 715 clock-names = "baudclk", "apb_pclk"; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 718 status = "disabled"; 719 }; 720 721 uart1: serial@20064000 { 722 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 723 reg = <0x20064000 0x100>; 724 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 725 reg-shift = <2>; 726 reg-io-width = <4>; 727 clock-frequency = <24000000>; 728 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 729 clock-names = "baudclk", "apb_pclk"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&uart1_xfer>; 732 status = "disabled"; 733 }; 734 735 uart2: serial@20068000 { 736 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 737 reg = <0x20068000 0x100>; 738 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 739 reg-shift = <2>; 740 reg-io-width = <4>; 741 clock-frequency = <24000000>; 742 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 743 clock-names = "baudclk", "apb_pclk"; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&uart2_xfer>; 746 status = "disabled"; 747 }; 748 749 i2c0: i2c@20072000 { 750 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 751 reg = <0x20072000 0x1000>; 752 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 clock-names = "i2c"; 756 clocks = <&cru PCLK_I2C0>; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&i2c0_xfer>; 759 status = "disabled"; 760 }; 761 762 spi: spi@20074000 { 763 compatible = "rockchip,rockchip-spi"; 764 reg = <0x20074000 0x1000>; 765 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>; 767 clock-names = "apb-pclk","spi_pclk"; 768 dmas = <&pdma 8>, <&pdma 9>; 769 dma-names = "tx", "rx"; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 pinctrl: pinctrl { 778 compatible = "rockchip,rk3036-pinctrl"; 779 rockchip,grf = <&grf>; 780 #address-cells = <1>; 781 #size-cells = <1>; 782 ranges; 783 784 gpio0: gpio0@2007c000 { 785 compatible = "rockchip,gpio-bank"; 786 reg = <0x2007c000 0x100>; 787 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 788 clock-names = "bus"; 789 clocks = <&cru PCLK_GPIO0>; 790 791 gpio-controller; 792 #gpio-cells = <2>; 793 794 interrupt-controller; 795 #interrupt-cells = <2>; 796 }; 797 798 gpio1: gpio1@20080000 { 799 compatible = "rockchip,gpio-bank"; 800 reg = <0x20080000 0x100>; 801 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 802 clock-names = "bus"; 803 clocks = <&cru PCLK_GPIO1>; 804 805 gpio-controller; 806 #gpio-cells = <2>; 807 808 interrupt-controller; 809 #interrupt-cells = <2>; 810 }; 811 812 gpio2: gpio2@20084000 { 813 compatible = "rockchip,gpio-bank"; 814 reg = <0x20084000 0x100>; 815 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 816 clock-names = "bus"; 817 clocks = <&cru PCLK_GPIO2>; 818 819 gpio-controller; 820 #gpio-cells = <2>; 821 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 }; 825 826 pcfg_pull_default: pcfg_pull_default { 827 bias-pull-pin-default; 828 }; 829 830 pcfg_pull_none: pcfg-pull-none { 831 bias-disable; 832 }; 833 834 pwm0 { 835 pwm0_pin: pwm0-pin { 836 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_default>; 837 }; 838 }; 839 840 pwm1 { 841 pwm1_pin: pwm1-pin { 842 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>; 843 }; 844 }; 845 846 pwm2 { 847 pwm2_pin: pwm2-pin { 848 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>; 849 }; 850 }; 851 852 pwm3 { 853 pwm3_pin: pwm3-pin { 854 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_default>; 855 }; 856 }; 857 858 sdmmc { 859 sdmmc_clk: sdmmc-clk { 860 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 861 }; 862 863 sdmmc_cmd: sdmmc-cmd { 864 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 865 }; 866 867 sdmmc_cd: sdmmc-cd { 868 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 869 }; 870 871 sdmmc_bus1: sdmmc-bus1 { 872 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; 873 }; 874 875 sdmmc_bus4: sdmmc-bus4 { 876 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 877 <1 RK_PC3 1 &pcfg_pull_default>, 878 <1 RK_PC4 1 &pcfg_pull_default>, 879 <1 RK_PC5 1 &pcfg_pull_default>; 880 }; 881 }; 882 883 sdio { 884 sdio_bus1: sdio-bus1 { 885 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; 886 }; 887 888 sdio_bus4: sdio-bus4 { 889 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, 890 <0 RK_PB4 1 &pcfg_pull_default>, 891 <0 RK_PB5 1 &pcfg_pull_default>, 892 <0 RK_PB6 1 &pcfg_pull_default>; 893 }; 894 895 sdio_cmd: sdio-cmd { 896 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; 897 }; 898 899 sdio_clk: sdio-clk { 900 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; 901 }; 902 }; 903 904 emmc { 905 /* 906 * We run eMMC at max speed; bump up drive strength. 907 * We also have external pulls, so disable the internal ones. 908 */ 909 emmc_clk: emmc-clk { 910 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 911 }; 912 913 emmc_cmd: emmc-cmd { 914 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; 915 }; 916 917 emmc_bus8: emmc-bus8 { 918 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 919 <1 RK_PD1 2 &pcfg_pull_default>, 920 <1 RK_PD2 2 &pcfg_pull_default>, 921 <1 RK_PD3 2 &pcfg_pull_default>, 922 <1 RK_PD4 2 &pcfg_pull_default>, 923 <1 RK_PD5 2 &pcfg_pull_default>, 924 <1 RK_PD6 2 &pcfg_pull_default>, 925 <1 RK_PD7 2 &pcfg_pull_default>; 926 }; 927 }; 928 929 spdif_tx { 930 spdif_out: spdif-out { 931 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_default>; 932 }; 933 }; 934 935 emac { 936 emac_xfer: emac-xfer { 937 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ 938 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ 939 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ 940 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ 941 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ 942 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ 943 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ 944 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ 945 }; 946 947 emac_mdio: emac-mdio { 948 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ 949 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ 950 }; 951 }; 952 953 i2c0 { 954 i2c0_xfer: i2c0-xfer { 955 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 956 <0 RK_PA1 1 &pcfg_pull_none>; 957 }; 958 }; 959 960 i2c1 { 961 i2c1_xfer: i2c1-xfer { 962 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 963 <0 RK_PA3 1 &pcfg_pull_none>; 964 }; 965 }; 966 967 i2c2 { 968 i2c2_xfer: i2c2-xfer { 969 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 970 <2 RK_PC5 1 &pcfg_pull_none>; 971 }; 972 }; 973 974 i2s { 975 i2s_mclk: i2s-mclk { 976 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>; 977 }; 978 i2s_sclk: i2s-sclk { 979 rockchip,pins = <1 RK_PA1 1 &pcfg_pull_default>; 980 }; 981 i2s_lrclkrx: i2s-lrclkrx { 982 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 983 }; 984 i2s_lrclktx: i2s-lrclktx { 985 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 986 }; 987 i2s_sdo: i2s-sdo { 988 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>; 989 }; 990 i2s_sdi: i2s-sdi { 991 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_default>; 992 }; 993 }; 994 995 hdmi { 996 hdmi_ctl: hdmi-ctl { 997 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, 998 <1 RK_PB1 1 &pcfg_pull_none>, 999 <1 RK_PB2 1 &pcfg_pull_none>, 1000 <1 RK_PB3 1 &pcfg_pull_none>; 1001 }; 1002 }; 1003 1004 uart0 { 1005 uart0_xfer: uart0-xfer { 1006 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 1007 <0 RK_PC1 1 &pcfg_pull_default>; 1008 }; 1009 1010 uart0_cts: uart0-cts { 1011 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; 1012 }; 1013 1014 uart0_rts: uart0-rts { 1015 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; 1016 }; 1017 }; 1018 1019 uart1 { 1020 uart1_xfer: uart1-xfer { 1021 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, 1022 <2 RK_PC7 1 &pcfg_pull_default>; 1023 }; 1024 /* no rts / cts for uart1 */ 1025 }; 1026 1027 uart2 { 1028 uart2_xfer: uart2-xfer { 1029 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1030 <1 RK_PC3 2 &pcfg_pull_default>; 1031 }; 1032 /* no rts / cts for uart2 */ 1033 }; 1034 1035 spi-pins { 1036 spi_txd:spi-txd { 1037 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1038 }; 1039 1040 spi_rxd:spi-rxd { 1041 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1042 }; 1043 1044 spi_clk:spi-clk { 1045 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1046 }; 1047 1048 spi_cs0:spi-cs0 { 1049 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1050 1051 }; 1052 1053 spi_cs1:spi-cs1 { 1054 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1055 1056 }; 1057 }; 1058 }; 1059}; 1060