1/* 2 * Copyright (c) 2013 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ or X11 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include "skeleton.dtsi" 11 12/ { 13 interrupt-parent = <&gic>; 14 15 aliases { 16 ethernet0 = &emac; 17 i2c0 = &i2c0; 18 i2c1 = &i2c1; 19 i2c2 = &i2c2; 20 i2c3 = &i2c3; 21 i2c4 = &i2c4; 22 mmc0 = &emmc; 23 mmc1 = &mmc0; 24 mmc2 = &mmc1; 25 serial0 = &uart0; 26 serial1 = &uart1; 27 serial2 = &uart2; 28 serial3 = &uart3; 29 spi0 = &spi0; 30 spi1 = &spi1; 31 }; 32 33 amba { 34 compatible = "simple-bus"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 ranges; 38 39 dmac1_s: dma-controller@20018000 { 40 compatible = "arm,pl330", "arm,primecell"; 41 reg = <0x20018000 0x4000>; 42 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 44 #dma-cells = <1>; 45 arm,pl330-broken-no-flushp; 46 clocks = <&cru ACLK_DMA1>; 47 clock-names = "apb_pclk"; 48 }; 49 50 dmac1_ns: dma-controller@2001c000 { 51 compatible = "arm,pl330", "arm,primecell"; 52 reg = <0x2001c000 0x4000>; 53 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 55 #dma-cells = <1>; 56 arm,pl330-broken-no-flushp; 57 clocks = <&cru ACLK_DMA1>; 58 clock-names = "apb_pclk"; 59 status = "disabled"; 60 }; 61 62 dmac2: dma-controller@20078000 { 63 compatible = "arm,pl330", "arm,primecell"; 64 reg = <0x20078000 0x4000>; 65 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 67 #dma-cells = <1>; 68 arm,pl330-broken-no-flushp; 69 clocks = <&cru ACLK_DMA2>; 70 clock-names = "apb_pclk"; 71 }; 72 }; 73 74 xin24m: oscillator { 75 compatible = "fixed-clock"; 76 clock-frequency = <24000000>; 77 #clock-cells = <0>; 78 clock-output-names = "xin24m"; 79 }; 80 81 L2: l2-cache-controller@10138000 { 82 compatible = "arm,pl310-cache"; 83 reg = <0x10138000 0x1000>; 84 cache-unified; 85 cache-level = <2>; 86 }; 87 88 scu@1013c000 { 89 compatible = "arm,cortex-a9-scu"; 90 reg = <0x1013c000 0x100>; 91 }; 92 93 global_timer: global-timer@1013c200 { 94 compatible = "arm,cortex-a9-global-timer"; 95 reg = <0x1013c200 0x20>; 96 interrupts = <GIC_PPI 11 0x304>; 97 clocks = <&cru CORE_PERI>; 98 }; 99 100 local_timer: local-timer@1013c600 { 101 compatible = "arm,cortex-a9-twd-timer"; 102 reg = <0x1013c600 0x20>; 103 interrupts = <GIC_PPI 13 0x304>; 104 clocks = <&cru CORE_PERI>; 105 }; 106 107 gic: interrupt-controller@1013d000 { 108 compatible = "arm,cortex-a9-gic"; 109 interrupt-controller; 110 #interrupt-cells = <3>; 111 reg = <0x1013d000 0x1000>, 112 <0x1013c100 0x0100>; 113 }; 114 115 uart0: serial@10124000 { 116 compatible = "snps,dw-apb-uart"; 117 reg = <0x10124000 0x400>; 118 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 119 reg-shift = <2>; 120 reg-io-width = <1>; 121 clock-names = "baudclk", "apb_pclk"; 122 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 123 status = "disabled"; 124 }; 125 126 uart1: serial@10126000 { 127 compatible = "snps,dw-apb-uart"; 128 reg = <0x10126000 0x400>; 129 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 130 reg-shift = <2>; 131 reg-io-width = <1>; 132 clock-names = "baudclk", "apb_pclk"; 133 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 134 status = "disabled"; 135 }; 136 137 noc: syscon@10128000 { 138 u-boot,dm-pre-reloc; 139 compatible = "rockchip,rk3188-noc", "syscon"; 140 reg = <0x10128000 0x2000>; 141 }; 142 143 usb_otg: usb@10180000 { 144 compatible = "rockchip,rk3066-usb", "snps,dwc2"; 145 reg = <0x10180000 0x40000>; 146 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru HCLK_OTG0>; 148 clock-names = "otg"; 149 dr_mode = "otg"; 150 g-np-tx-fifo-size = <16>; 151 g-rx-fifo-size = <275>; 152 g-tx-fifo-size = <256 128 128 64 64 32>; 153 g-use-dma; 154 phys = <&usbphy0>; 155 phy-names = "usb2-phy"; 156 status = "disabled"; 157 }; 158 159 usb_host: usb@101c0000 { 160 compatible = "snps,dwc2"; 161 reg = <0x101c0000 0x40000>; 162 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&cru HCLK_OTG1>; 164 clock-names = "otg"; 165 dr_mode = "host"; 166 phys = <&usbphy1>; 167 phy-names = "usb2-phy"; 168 status = "disabled"; 169 }; 170 171 emac: ethernet@10204000 { 172 compatible = "snps,arc-emac"; 173 reg = <0x10204000 0x3c>; 174 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 178 rockchip,grf = <&grf>; 179 180 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 181 clock-names = "hclk", "macref"; 182 max-speed = <100>; 183 phy-mode = "rmii"; 184 185 status = "disabled"; 186 }; 187 188 mmc0: dwmmc@10214000 { 189 compatible = "rockchip,rk2928-dw-mshc"; 190 reg = <0x10214000 0x1000>; 191 max-frequency = <37500000>; 192 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 194 clock-names = "biu", "ciu"; 195 fifo-depth = <256>; 196 status = "disabled"; 197 }; 198 199 mmc1: dwmmc@10218000 { 200 compatible = "rockchip,rk2928-dw-mshc"; 201 reg = <0x10218000 0x1000>; 202 max-frequency = <37500000>; 203 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 205 clock-names = "biu", "ciu"; 206 fifo-depth = <256>; 207 status = "disabled"; 208 }; 209 210 emmc: dwmmc@1021c000 { 211 compatible = "rockchip,rk2928-dw-mshc"; 212 reg = <0x1021c000 0x1000>; 213 max-frequency = <37500000>; 214 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 216 clock-names = "biu", "ciu"; 217 fifo-depth = <256>; 218 status = "disabled"; 219 }; 220 221 pmu: pmu@20004000 { 222 compatible = "rockchip,rk3066-pmu", "syscon"; 223 reg = <0x20004000 0x100>; 224 u-boot,dm-pre-reloc; 225 }; 226 227 grf: grf@20008000 { 228 compatible = "syscon"; 229 reg = <0x20008000 0x200>; 230 u-boot,dm-pre-reloc; 231 }; 232 233 dmc: dmc@20020000 { 234 /* unreviewed u-boot-specific binding */ 235 compatible = "rockchip,rk3188-dmc", "syscon"; 236 rockchip,cru = <&cru>; 237 rockchip,grf = <&grf>; 238 rockchip,pmu = <&pmu>; 239 rockchip,noc = <&noc>; 240 reg = <0x20020000 0x3fc 241 0x20040000 0x294>; 242 clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>; 243 clock-names = "pclk_ddrupctl", "pclk_publ"; 244 u-boot,dm-pre-reloc; 245 }; 246 247 i2c0: i2c@2002d000 { 248 compatible = "rockchip,rk3066-i2c"; 249 reg = <0x2002d000 0x1000>; 250 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 254 rockchip,grf = <&grf>; 255 256 clock-names = "i2c"; 257 clocks = <&cru PCLK_I2C0>; 258 259 status = "disabled"; 260 }; 261 262 i2c1: i2c@2002f000 { 263 compatible = "rockchip,rk3066-i2c"; 264 reg = <0x2002f000 0x1000>; 265 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 rockchip,grf = <&grf>; 270 271 clocks = <&cru PCLK_I2C1>; 272 clock-names = "i2c"; 273 274 status = "disabled"; 275 }; 276 277 pwm0: pwm@20030000 { 278 compatible = "rockchip,rk2928-pwm"; 279 reg = <0x20030000 0x10>; 280 #pwm-cells = <2>; 281 clocks = <&cru PCLK_PWM01>; 282 status = "disabled"; 283 }; 284 285 pwm1: pwm@20030010 { 286 compatible = "rockchip,rk2928-pwm"; 287 reg = <0x20030010 0x10>; 288 #pwm-cells = <2>; 289 clocks = <&cru PCLK_PWM01>; 290 status = "disabled"; 291 }; 292 293 wdt: watchdog@2004c000 { 294 compatible = "snps,dw-wdt"; 295 reg = <0x2004c000 0x100>; 296 clocks = <&cru PCLK_WDT>; 297 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 298 status = "disabled"; 299 }; 300 301 pwm2: pwm@20050020 { 302 compatible = "rockchip,rk2928-pwm"; 303 reg = <0x20050020 0x10>; 304 #pwm-cells = <2>; 305 clocks = <&cru PCLK_PWM23>; 306 status = "disabled"; 307 }; 308 309 pwm3: pwm@20050030 { 310 compatible = "rockchip,rk2928-pwm"; 311 reg = <0x20050030 0x10>; 312 #pwm-cells = <2>; 313 clocks = <&cru PCLK_PWM23>; 314 status = "disabled"; 315 }; 316 317 i2c2: i2c@20056000 { 318 compatible = "rockchip,rk3066-i2c"; 319 reg = <0x20056000 0x1000>; 320 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 324 rockchip,grf = <&grf>; 325 326 clocks = <&cru PCLK_I2C2>; 327 clock-names = "i2c"; 328 329 status = "disabled"; 330 }; 331 332 i2c3: i2c@2005a000 { 333 compatible = "rockchip,rk3066-i2c"; 334 reg = <0x2005a000 0x1000>; 335 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 339 rockchip,grf = <&grf>; 340 341 clocks = <&cru PCLK_I2C3>; 342 clock-names = "i2c"; 343 344 status = "disabled"; 345 }; 346 347 i2c4: i2c@2005e000 { 348 compatible = "rockchip,rk3066-i2c"; 349 reg = <0x2005e000 0x1000>; 350 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 354 rockchip,grf = <&grf>; 355 356 clocks = <&cru PCLK_I2C4>; 357 clock-names = "i2c"; 358 359 status = "disabled"; 360 }; 361 362 uart2: serial@20064000 { 363 compatible = "snps,dw-apb-uart"; 364 reg = <0x20064000 0x400>; 365 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 366 reg-shift = <2>; 367 reg-io-width = <1>; 368 clock-frequency = <24000000>; 369 clock-names = "baudclk", "apb_pclk"; 370 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 371 status = "disabled"; 372 }; 373 374 uart3: serial@20068000 { 375 compatible = "snps,dw-apb-uart"; 376 reg = <0x20068000 0x400>; 377 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 378 reg-shift = <2>; 379 reg-io-width = <1>; 380 clock-names = "baudclk", "apb_pclk"; 381 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 382 status = "disabled"; 383 }; 384 385 saradc: saradc@2006c000 { 386 compatible = "rockchip,saradc"; 387 reg = <0x2006c000 0x100>; 388 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 389 #io-channel-cells = <1>; 390 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 391 clock-names = "saradc", "apb_pclk"; 392 status = "disabled"; 393 }; 394 395 spi0: spi@20070000 { 396 compatible = "rockchip,rk3066-spi"; 397 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 398 clock-names = "spiclk", "apb_pclk"; 399 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 400 reg = <0x20070000 0x1000>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 dmas = <&dmac2 10>, <&dmac2 11>; 404 dma-names = "tx", "rx"; 405 status = "disabled"; 406 }; 407 408 spi1: spi@20074000 { 409 compatible = "rockchip,rk3066-spi"; 410 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 411 clock-names = "spiclk", "apb_pclk"; 412 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 413 reg = <0x20074000 0x1000>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 dmas = <&dmac2 12>, <&dmac2 13>; 417 dma-names = "tx", "rx"; 418 status = "disabled"; 419 }; 420}; 421