xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/spi-rockchip.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Rockchip SPI Controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyundescription:
10*4882a593Smuzhiyun  The Rockchip SPI controller is used to interface with various devices such
11*4882a593Smuzhiyun  as flash and display controllers using the SPI communication interface.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunallOf:
14*4882a593Smuzhiyun  - $ref: "spi-controller.yaml#"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunmaintainers:
17*4882a593Smuzhiyun  - Heiko Stuebner <heiko@sntech.de>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun# Everything else is described in the common file
20*4882a593Smuzhiyunproperties:
21*4882a593Smuzhiyun  compatible:
22*4882a593Smuzhiyun    oneOf:
23*4882a593Smuzhiyun      - const: rockchip,rk3036-spi
24*4882a593Smuzhiyun      - const: rockchip,rk3066-spi
25*4882a593Smuzhiyun      - const: rockchip,rk3228-spi
26*4882a593Smuzhiyun      - const: rockchip,rv1108-spi
27*4882a593Smuzhiyun      - items:
28*4882a593Smuzhiyun          - enum:
29*4882a593Smuzhiyun              - rockchip,px30-spi
30*4882a593Smuzhiyun              - rockchip,rk3188-spi
31*4882a593Smuzhiyun              - rockchip,rk3288-spi
32*4882a593Smuzhiyun              - rockchip,rk3308-spi
33*4882a593Smuzhiyun              - rockchip,rk3328-spi
34*4882a593Smuzhiyun              - rockchip,rk3368-spi
35*4882a593Smuzhiyun              - rockchip,rk3399-spi
36*4882a593Smuzhiyun              - rockchip,rv1126-spi
37*4882a593Smuzhiyun          - const: rockchip,rk3066-spi
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  reg:
40*4882a593Smuzhiyun    maxItems: 1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  interrupts:
43*4882a593Smuzhiyun    maxItems: 1
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  clocks:
46*4882a593Smuzhiyun    items:
47*4882a593Smuzhiyun      - description: transfer-clock
48*4882a593Smuzhiyun      - description: peripheral clock
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  clock-names:
51*4882a593Smuzhiyun    items:
52*4882a593Smuzhiyun      - const: spiclk
53*4882a593Smuzhiyun      - const: apb_pclk
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun  dmas:
56*4882a593Smuzhiyun    items:
57*4882a593Smuzhiyun      - description: TX DMA Channel
58*4882a593Smuzhiyun      - description: RX DMA Channel
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun  dma-names:
61*4882a593Smuzhiyun    items:
62*4882a593Smuzhiyun      - const: tx
63*4882a593Smuzhiyun      - const: rx
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun  rx-sample-delay-ns:
66*4882a593Smuzhiyun    default: 0
67*4882a593Smuzhiyun    description:
68*4882a593Smuzhiyun      Nano seconds to delay after the SCLK edge before sampling Rx data
69*4882a593Smuzhiyun      (may need to be fine tuned for high capacitance lines).
70*4882a593Smuzhiyun      If not specified 0 will be used.
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun  csm:
73*4882a593Smuzhiyun    default: 0
74*4882a593Smuzhiyun    description:
75*4882a593Smuzhiyun      ss_n be high for half or one sclk_out cycle after every frame data
76*4882a593Smuzhiyun      is transferred.
77*4882a593Smuzhiyun      If not specified 0 will be used.
78*4882a593Smuzhiyun    enum:
79*4882a593Smuzhiyun      - 0 # keep low
80*4882a593Smuzhiyun      - 1 # half sclk_out
81*4882a593Smuzhiyun      - 2 # one sclk_out
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun  pinctrl-names:
84*4882a593Smuzhiyun    minItems: 1
85*4882a593Smuzhiyun    items:
86*4882a593Smuzhiyun      - const: default
87*4882a593Smuzhiyun      - const: sleep
88*4882a593Smuzhiyun    description:
89*4882a593Smuzhiyun      Names for the pin configuration(s); may be "default" or "sleep",
90*4882a593Smuzhiyun      where the "sleep" configuration may describe the state
91*4882a593Smuzhiyun      the pins should be in during system suspend.
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun  rockchip,poll-only:
94*4882a593Smuzhiyun    description: Add this property to set the transmission method as CPU polling.
95*4882a593Smuzhiyun    type: boolean
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun  rockchip,cs-inactive-disable:
98*4882a593Smuzhiyun    description: Add this property to disable the cs inactive interrupt for spi
99*4882a593Smuzhiyun      slave.
100*4882a593Smuzhiyun    type: boolean
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun  ready-gpios:
103*4882a593Smuzhiyun    description: GPIO spec for the spi slave ready signal.
104*4882a593Smuzhiyun    maxItems: 1
105*4882a593Smuzhiyun
106*4882a593Smuzhiyunrequired:
107*4882a593Smuzhiyun  - compatible
108*4882a593Smuzhiyun  - reg
109*4882a593Smuzhiyun  - interrupts
110*4882a593Smuzhiyun  - clocks
111*4882a593Smuzhiyun  - clock-names
112*4882a593Smuzhiyun
113*4882a593SmuzhiyununevaluatedProperties: false
114*4882a593Smuzhiyun
115*4882a593Smuzhiyunexamples:
116*4882a593Smuzhiyun  - |
117*4882a593Smuzhiyun    #include <dt-bindings/clock/rk3188-cru-common.h>
118*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
119*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/irq.h>
120*4882a593Smuzhiyun    spi0: spi@ff110000 {
121*4882a593Smuzhiyun      compatible = "rockchip,rk3066-spi";
122*4882a593Smuzhiyun      reg = <0xff110000 0x1000>;
123*4882a593Smuzhiyun      interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
124*4882a593Smuzhiyun      clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
125*4882a593Smuzhiyun      clock-names = "spiclk", "apb_pclk";
126*4882a593Smuzhiyun      dmas = <&pdma1 11>, <&pdma1 12>;
127*4882a593Smuzhiyun      dma-names = "tx", "rx";
128*4882a593Smuzhiyun      pinctrl-0 = <&spi1_pins>;
129*4882a593Smuzhiyun      pinctrl-1 = <&spi1_sleep>;
130*4882a593Smuzhiyun      pinctrl-names = "default", "sleep";
131*4882a593Smuzhiyun      rx-sample-delay-ns = <10>;
132*4882a593Smuzhiyun      #address-cells = <1>;
133*4882a593Smuzhiyun      #size-cells = <0>;
134*4882a593Smuzhiyun    };
135