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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
37 MAC Interface Impedance control to set the programmable output impedance
40 ti,max-output-impedance:
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddra71-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
7 #include "dra7-mmc-iodelay.dtsi"
8 #include "dra72x-mmc-iodelay.dtsi"
9 #include <dt-bindings/net/ti-dp83867.h>
12 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
25 ipu2_memory_region: ipu2-memory@95800000 {
[all …]
H A Ddra72-evm-revc.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 #include <dt-bindings/net/ti-dp83867.h>
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
30 compatible = "shared-dma-pool";
[all …]
H A Ddra76-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-evm-common.dtsi"
9 #include "dra76x-mmc-iodelay.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
14 compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
28 reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
H A Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
26 dsp_common_memory: dsp-common-memory@81f800000 {
[all …]
H A Dqcom-apq8060-dragonboard.dts23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
26 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
27 #include "qcom-msm8660.dtsi"
31 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
38 stdout-path = "serial0:115200n8";
42 compatible = "simple-bus";
45 vph: regulator-fixed {
46 compatible = "regulator-fixed";
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Ddra71-evm.dts2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
9 #include "dra72-evm-common.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
21 vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
22 compatible = "regulator-gpio";
24 regulator-name = "vddshv8";
25 regulator-min-microvolt = <1800000>;
26 regulator-max-microvolt = <3000000>;
27 regulator-boot-on;
[all …]
H A Drk3288-tinker.dtsi2 * This file is dual-licensed: you can use it either under the terms
42 #include "rk3288-u-boot.dtsi"
50 ext_gmac: external-gmac-clock {
51 compatible = "fixed-clock";
52 clock-frequency = <125000000>;
53 clock-output-names = "ext_gmac";
54 #clock-cells = <0>;
57 gpio-keys {
58 compatible = "gpio-keys";
59 #address-cells = <1>;
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dnau8825.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
34 #define NUVOTON_CODEC_DAI "nau8825-hifi"
64 /* scaling for mclk from sysclk_src output */
238 * nau8825_sema_acquire - acquire the semaphore of nau88l25
248 * this function returns -ETIME. If the sleep is interrupted by a signal,
249 * this function will return -EINTR. It returns 0 if the semaphore was
261 ret = down_timeout(&nau8825->xtalk_sem, timeout); in nau8825_sema_acquire()
263 dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); in nau8825_sema_acquire()
265 ret = down_trylock(&nau8825->xtalk_sem); in nau8825_sema_acquire()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
20 * The higher 16-bit of this register is used for write protection
98 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
99 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
103 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
104 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
113 rate = clk_get_rate(rk_phy->emmcclk); in rockchip_emmc_phy_power()
138 rate - ideal_rate : ideal_rate - rate; in rockchip_emmc_phy_power()
143 * far off. Also warn if we're above the 200 MHz max. Don't in rockchip_emmc_phy_power()
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dti.c4 * SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/net/ti-dp83867.h>
83 /* User setting - can be taken from DTS */
102 * phy_read_mmd_indirect - reads data from the MMD registers
119 int value = -1; in phy_read_mmd_indirect()
136 * phy_write_mmd_indirect - writes data to the MMD registers
169 * dp83867_data_init - Convenience function for setting PHY specific data
175 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
176 struct udevice *dev = phydev->dev; in dp83867_of_init()
178 const void *fdt = gd->fdt_blob; in dp83867_of_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <dt-bindings/net/ti-dp83867.h>
184 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
191 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
196 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
197 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
200 return -EINVAL; in dp83867_set_wol()
214 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
216 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
218 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
[all …]
H A Ddp83869.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/net/ti-dp83869.h>
69 /* This is the same bit mask as the BMCR so re-use the BMCR default */
157 struct dp83869_private *dp83869 = phydev->priv; in dp83869_read_status()
164 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) { in dp83869_read_status()
165 if (phydev->link) { in dp83869_read_status()
166 if (dp83869->mode == DP83869_RGMII_100_BASE) in dp83869_read_status()
167 phydev->speed = SPEED_100; in dp83869_read_status()
169 phydev->speed = SPEED_UNKNOWN; in dp83869_read_status()
170 phydev->duplex = DUPLEX_UNKNOWN; in dp83869_read_status()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-puma.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pwm/pwm.h>
8 #include "rk3399-opp.dtsi"
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&module_led_pin>;
16 module_led: led-0 {
19 linux,default-trigger = "heartbeat";
20 panic-indicator;
25 * Overwrite the opp-table for CPUB as this board uses a different
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c6 * SPDX-License-Identifier: GPL-2.0+
32 writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); in reset_phy_ctrl()
33 writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); in reset_phy_ctrl()
51 /* Set Impedance Output Driver */ in ddr3_mem_ctrl_init()
52 val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
53 (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
54 (mem->impedance << CA_CS_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
55 (mem->impedance << CA_ADR_DRVR_DS_OFFSET); in ddr3_mem_ctrl_init()
56 writel(val, &phy0_ctrl->phy_con39); in ddr3_mem_ctrl_init()
57 writel(val, &phy1_ctrl->phy_con39); in ddr3_mem_ctrl_init()
[all …]
/OK3568_Linux_fs/kernel/sound/usb/
H A Dmixer_scarlett.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * Auto-detection via UAC2 is not feasible to properly discover the vast
38 * - change Impedance of inputs (Line-in, Mic / Instrument, Hi-Z)
39 * - select clock source
40 * - dynamic input to mixer-matrix assignment
41 * - 18 x 6 mixer-matrix gain stages
42 * - bus routing & volume control
43 * - automatic re-initialization on connect if device was power-cycled
47 * 0x01 Analog Input line/instrument impedance switch, wValue=0x0901 +
49 * pad (-10dB) switch, wValue=0x0b01 + channel, data=Off/On (2bytes)
[all …]
/OK3568_Linux_fs/kernel/drivers/extcon/
H A Dextcon-arizona.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * extcon-arizona.c - Extcon driver Wolfson Arizona devices
5 * Copyright (C) 2012-2014 Wolfson Microelectronics plc
21 #include <linux/extcon-provider.h>
28 #include <dt-bindings/mfd/arizona.h>
111 { .max = 11, .key = BTN_0 },
112 { .max = 28, .key = BTN_1 },
113 { .max = 54, .key = BTN_2 },
114 { .max = 100, .key = BTN_3 },
115 { .max = 186, .key = BTN_4 },
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
174 if (!popts->memctl_interleaving) in set_csn_config()
176 switch (popts->memctl_interleaving_mode) { in set_csn_config()
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
36 /*-----------------------------------------------------------*/
114 for (; timeout > 0; timeout--) { in comphy_poll_reg()
142 * 1. Enable max PLL. in comphy_pcie_power_up()
171 * 6. Enable the output of 100M/125M/500M clock in comphy_pcie_power_up()
256 * 1. Select 40-bit data width width in comphy_sata_power_up()
287 * 5. Set vendor-specific configuration (??) in comphy_sata_power_up()
335 /* set PRD_TXDEEMPH (3.5db de-emph) */ in comphy_usb3_power_up()
340 * low impedance mode during electrical idle in comphy_usb3_power_up()
[all …]
H A Dcomphy_cp110.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
79 } while (data != val && --usec_timout > 0); in polling_with_timeout()
101 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
103 * U-Boot to mainline version. in comphy_pcie_power_up()
105 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
106 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()
126 * If PCIe clock is output and clock source from SerDes lane 5, in comphy_pcie_power_up()
127 * we need to configure the clock-source MUX. in comphy_pcie_power_up()
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A DMPC837XERDB.h6 * SPDX-License-Identifier: GPL-2.0+
25 * On-board devices
84 /* System performance - define the value i.e. CONFIG_SYS_XXX
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
92 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
95 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
96 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
97 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
106 * Output Buffer Impedance
[all …]
H A DMPC837XEMDS.h5 * SPDX-License-Identifier: GPL-2.0+
96 * Output Buffer Impedance
132 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
133 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
210 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
249 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
326 * Config on-board RTC
333 * Addresses are mapped 1-1.
412 /* Options are: TSEC[0-1] */
[all …]
/OK3568_Linux_fs/kernel/include/sound/
H A Dhda_verbs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * HD-audio codec verbs
59 /* f10-f1a: GPIO */
162 #define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
163 #define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
164 #define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
252 #define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */
256 #define AC_PINCAP_OUT (1<<4) /* output capable */
264 * in HD-audio specification
275 #define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c4 * SPDX-License-Identifier: GPL-2.0
18 #define ENDED_OK "High speed PHY - Ended Successfully\n"
193 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val]; in board_serdes_cfg_get()
214 return (info->line0_7 >> (line_num << 2)) & 0xF; in get_line_cfg()
216 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; in get_line_cfg()
236 * non-established PCIe links (link down). Especially under certain
238 * To enable a board-specific detection pulse width this weak
240 * overwritten if needed by a board-specific version. If the board
241 * code does not provide a non-weak version of this variable, the
270 * Get max. serdes lines count in serdes_phy_config()
[all …]

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