4  * SPDX-License-Identifier:	GPL-2.0
14 #include <dt-bindings/net/ti-dp83867.h>
83 /* User setting - can be taken from DTS */
102  * phy_read_mmd_indirect - reads data from the MMD registers
119 	int value = -1;  in phy_read_mmd_indirect()
136  * phy_write_mmd_indirect - writes data to the MMD registers
169  * dp83867_data_init - Convenience function for setting PHY specific data
175 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_of_init()
176 	struct udevice *dev = phydev->dev;  in dp83867_of_init()
178 	const void *fdt = gd->fdt_blob;  in dp83867_of_init()
180 	if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))  in dp83867_of_init()
181 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;  in dp83867_of_init()
182 	else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))  in dp83867_of_init()
183 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;  in dp83867_of_init()
185 		dp83867->io_impedance = -EINVAL;  in dp83867_of_init()
187 	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),  in dp83867_of_init()
188 				 "ti,rx-internal-delay", -1);  in dp83867_of_init()
190 	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),  in dp83867_of_init()
191 				 "ti,tx-internal-delay", -1);  in dp83867_of_init()
193 	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),  in dp83867_of_init()
194 				 "ti,fifo-depth", -1);  in dp83867_of_init()
201 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_of_init()
203 	dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;  in dp83867_of_init()
204 	dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;  in dp83867_of_init()
205 	dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;  in dp83867_of_init()
206 	dp83867->io_impedance = -EINVAL;  in dp83867_of_init()
218 	if (!phydev->priv) {  in dp83867_config()
221 			return -ENOMEM;  in dp83867_config()
223 		phydev->priv = dp83867;  in dp83867_config()
228 		dp83867 = (struct dp83867_private *)phydev->priv;  in dp83867_config()
239 			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));  in dp83867_config()
246 		cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);  in dp83867_config()
256 				       DP83867_DEVADDR, phydev->addr, 0x0);  in dp83867_config()
262 			  (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |  in dp83867_config()
263 			  (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));  in dp83867_config()
269 					    DP83867_DEVADDR, phydev->addr);  in dp83867_config()
271 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)  in dp83867_config()
275 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)  in dp83867_config()
278 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)  in dp83867_config()
282 				       DP83867_DEVADDR, phydev->addr, val);  in dp83867_config()
284 		delay = (dp83867->rx_id_delay |  in dp83867_config()
285 			 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));  in dp83867_config()
288 				       DP83867_DEVADDR, phydev->addr, delay);  in dp83867_config()
290 		if (dp83867->io_impedance >= 0) {  in dp83867_config()
294 						    phydev->addr);  in dp83867_config()
296 			val |= dp83867->io_impedance &  in dp83867_config()
299 					       DP83867_DEVADDR, phydev->addr,  in dp83867_config()