include/configs/MPC837XERDB.h

6  * SPDX-License-Identifier:	GPL-2.0+
25  * On-board devices
84 /* System performance - define the value i.e. CONFIG_SYS_XXX
88 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
89 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
92 #define CONFIG_SYS_SPCR_TSECEP	3	/* eTSEC1&2 emergency priority (0-3) */
95 #define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
96 #define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
97 #define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
106  * Output Buffer Impedance
234 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
250 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
272 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
352  * Config on-board RTC
359  * Addresses are mapped 1-1.
429 /* Options are: TSEC[0-1] */
463 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
505 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
545 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
557 /* L2 Switch: cache-inhibit and guarded */
569 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
603 /* PCI MMIO space: cache-inhibit and guarded */
644 				/* U-Boot image on TFTP server */
645 #define CONFIG_UBOOTPATH	"u-boot.bin"
683 	"bootm $loadaddr - $fdtaddr"